2.4.1. Privilege Levels

Nios® V Processor Reference Manual

Download PDF

ID 683632

Date 10/31/2022

Version

Public

A newer version of this document is available. Customers should click here to go to the newest version.

Visible to Intel only — GUID: xla1629681481097

Ixiasoft

View Details

Document Table of Contents

Document Table of Contents x

1. Overview 2. Nios® V/m Processor 3. Nios V Processor Reference Manual Archives 4. Document Revision History for the Nios® V Processor Reference Manual

1. Overview x

1.1. Intel® Quartus® Prime Software Support

2. Nios® V/m Processor x

2.1. Processor Performance Benchmarks 2.2. Processor Pipeline 2.3. Processor Architecture 2.4. Programming Model 2.5. Core Implementation

2.3. Processor Architecture x

2.3.1. General-Purpose Register File 2.3.2. Arithmetic Logic Unit 2.3.3. Reset and Debug Signals 2.3.4. Control and Status Registers 2.3.5. Exception Controller 2.3.6. Interrupt Controller 2.3.7. Memory and I/O Organization 2.3.8. RISC-V based Debug Module

2.3.6. Interrupt Controller x

2.3.6.1. Timer and Software Interrupt Module

2.3.7. Memory and I/O Organization x

2.3.7.1. Instruction and Data Buses

2.3.7.1. Instruction and Data Buses x

2.3.7.1.1. Instruction Manager Port 2.3.7.1.2. Data Manager Port 2.3.7.1.3. Address Map

2.3.8. RISC-V based Debug Module x

2.3.8.1. Debug Mode 2.3.8.2. Halt from Debug Module 2.3.8.3. Trigger 2.3.8.4. Abstract Commands in Debug Mode 2.3.8.5. Hardware/Software Interface

2.4. Programming Model x

2.4.1. Privilege Levels 2.4.2. Control and Status Registers (CSR) Mapping

2.4.1. Privilege Levels x

2.4.1.1. Machine Mode (M-mode) 2.4.1.2. Debug Mode (D-mode)

2.4.2. Control and Status Registers (CSR) Mapping x

2.4.2.1. Control and Status Register Field

2.5. Core Implementation x

2.5.1. Instruction Set Reference

1. Overview

1.1. Intel® Quartus® Prime Software Support

2. Nios® V/m Processor

2.1. Processor Performance Benchmarks

2.2. Processor Pipeline

2.3. Processor Architecture

2.3.1. General-Purpose Register File

2.3.2. Arithmetic Logic Unit

2.3.3. Reset and Debug Signals

2.3.4. Control and Status Registers

2.3.5. Exception Controller

2.3.6. Interrupt Controller

2.3.6.1. Timer and Software Interrupt Module

2.3.7. Memory and I/O Organization

2.3.7.1. Instruction and Data Buses

2.3.7.1.1. Instruction Manager Port

2.3.7.1.2. Data Manager Port

2.3.7.1.3. Address Map

2.3.8. RISC-V based Debug Module

2.3.8.1. Debug Mode

2.3.8.2. Halt from Debug Module

2.3.8.3. Trigger

2.3.8.4. Abstract Commands in Debug Mode

2.3.8.5. Hardware/Software Interface

2.4. Programming Model

2.4.1. Privilege Levels

2.4.1.1. Machine Mode (M-mode)

2.4.1.2. Debug Mode (D-mode)

2.4.2. Control and Status Registers (CSR) Mapping

2.4.2.1. Control and Status Register Field

2.5. Core Implementation

2.5.1. Instruction Set Reference

3. Nios V Processor Reference Manual Archives

4. Document Revision History for the Nios® V Processor Reference Manual

Visible to Intel only — GUID: xla1629681481097

Ixiasoft

View Details