F-Tile Interlaken Intel® FPGA IP User Guide

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ID 683622
Date 12/04/2023
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile Interlaken Intel® FPGA IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. IP Registers 7. F-Tile Interlaken Intel® FPGA IP User Guide Archives 8. Document Revision History for F-Tile Interlaken Intel FPGA IP User Guide
1. About the F-Tile Interlaken Intel® FPGA IP Core x
1.1. Features 1.2. Device Family Support 1.3. Device Speed Grade Support 1.4. Performance and Resource Utilization 1.5. Round-trip Latency 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Generated File Structure 2.3. Specifying the IP Core Parameters and Options 2.4. Analog Parameter Settings 2.5. Reference and System PLL Clock for your IP Design 2.6. Simulating the IP Core 2.7. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Reference and System PLL Clock for your IP Design x
2.5.1. System PLL Configuration
4. Functional Description x
4.1. Data Path Flow 4.2. Interlaken Look-aside Data Path Flow 4.3. Modes of Operation 4.4. Performance 4.5. IP Reset 4.6. M20K ECC Support 4.7. Out-of-Band Flow Control 4.8. 32-bit Soft CWBIN Counters
4.1. Data Path Flow x
4.1.1. Interlaken TX Path 4.1.2. Interlaken RX Path
4.1.1. Interlaken TX Path x
4.1.1.1. Transmit Path Blocks 4.1.1.2. In-Band Calendar Bits on Transmit Side
4.1.2. Interlaken RX Path x
4.1.2.1. Receive Path Blocks 4.1.2.2. In-Band Calendar Bits on Receive Side 4.1.2.3. RX Errored Packet Handling
4.1.2.3. RX Errored Packet Handling x
4.1.2.3.1. Example With Errors and In-Band Calendar Bits
4.2. Interlaken Look-aside Data Path Flow x
4.2.1. Interlaken Look-aside TX Path 4.2.2. Interlaken Look-aside RX Path
4.2.1. Interlaken Look-aside TX Path x
4.2.1.1. Transmit Path Blocks
4.2.2. Interlaken Look-aside RX Path x
4.2.2.1. Receive Path Blocks 4.2.2.2. RX Error Handling
4.3. Modes of Operation x
4.3.1. Interleaved and Packet Modes 4.3.2. Multi-Segment Mode 4.3.3. Interlaken Look-aside Mode
4.3.1. Interleaved and Packet Modes x
4.3.1.1. Transmit User Data Interface Examples 4.3.1.2. Receive User Data Interface Example
4.3.2. Multi-Segment Mode x
4.3.2.1. Multi-Segment Interface Example
4.3.3. Interlaken Look-aside Mode x
4.3.3.1. Transmit User Data Interface Example 4.3.3.2. Receive User Data Interface Example
5. Interface Signals x
5.1. Clock and Reset Interface Signals 5.2. Transmit User Interface Signals 5.3. Receive User Interface Signals 5.4. Management Interface Signals 5.5. Reconfiguration Interface Signals 5.6. Interlaken Link and Miscellaneous Signals
1. About the F-Tile Interlaken Intel® FPGA IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. IP Registers
7. F-Tile Interlaken Intel® FPGA IP User Guide Archives
8. Document Revision History for F-Tile Interlaken Intel FPGA IP User Guide

1.4. Performance and Resource Utilization

This section covers the resources and expected performance numbers for selected variations of the Interlaken IP core using the Quartus® Prime Pro Edition software. Your results may slightly vary depending on the device you select.

For a comprehensive list of supported configurations, refer to Table 1. IP Supported Combinations of Number of Lanes and Data Rates

Table 4.  Resource Utilization for Interleaved Mode (number of segments = 1)The following numbers were obtained using the Quartus® Prime Pro Edition software version 23.4
Transceiver Mode PMA Type Data Rate (Gbps) Number of Lanes Resource Utilization
ALMs Logic Registers M20K Blocks
Primary Secondary
NRZ FGT 6.25 4 18462.1 41,093 7,863 28
10.3125 8 37743.9 76,489 13,690 52
12 58116.7 112,561 19,257 73
12.5 4 118480.5 41,134 7,816 28
8 37763.5 76,827 13,278 52
10 47651.6 94,214 16,538 61
12 58144.7 112,746 19,063 73
25.78125 4 18665.7 41,793 7,994 28
6 29524.6 63,817 11,663 52
8 37991.4 77,658 14,051 52
10 52907.9 109,744 18,785 100
12 62799.2 126,812 21,362 100
PAM4 FGT 26.5625 2 18296.4 45,463 8,952 28
2 (efifo) 18543.8 46,109 8,680 28
4 36932.9 84,420 15,963 52
4 (efifo) 37650.7 85,065 16.072 52
6 61780.6 137,219 23,811 100
6 (efifo) 61828.0 137,846 24,234 100
8 80873.2 178,831 30,499 100
8 (efifo) 82412.9 179,739 31,148 100
10 106017.7 229,249 37,882 121
10 (efifo) 107973.5 231,225 37,705 121
12 (EW=24)

132360.6

 285,599 44,856 148

12 (efifo) (EW=24)

134493.3

 287,189

44,866

148
12 (EW=32) 139817.9 306,559 47,305 196
12 (efifo) (EW=32) 142062.7 308,289 47,737 196
28.125 10 106734.0 228,843 37.714 121
10 (efifo) 107890.2 231,011 37,887 121
12 (EW=24) 133359.2 285,547 44,142 148
12 (efifo) (EW=24) 134518.7 285.633 45,074 148
12 (EW=32) 140775.5 305,761 47,299 196
12 (efifo) (EW=32) 142034.9 307,791 47,684 196
FHT 26.5625 1 (efifo) 18539.9 46,067 8,762 28
2 (efifo) 37629.5 84,751 16,430 52
3 (efifo) 61829.7 137,788 24,214 100
4 (efifo) 82397.2 179,258 30,564 100
Table 5.  Resource Utilization for Packet ModeThe following numbers were obtained using the Quartus® Prime Pro Edition software version 23.4
Transceiver Mode PMA Type Data Rate (Gbps) Number of Lanes Resource Utilization
ALMs Logic Registers M20K Blocks
Primary Secondary
NRZ FGT 6.25 4 18542.6 41,272 7,736 28
10.3125 8 37767.7 76,447 13,657 52
12 58150.6 113,007 18,864 73
12.5 4 18517.2 41,130 7,867 28
8 37698.1 76,563 13,567 52
10 47660.2 94,433 16,285 61
12 58181.0 112,874 19,004 73
25.78125 4 18678.7 41,688 8,120 28
6 29549.1 63,918 11,637 52
8 37974.6 77,398 14,393 52
10 52993.2 110,193 18,286 100
12 62918.1 126,913 21,487 100
PAM4 FGT 26.5625 2 18261.4 45,597 8,795 28
2 (efifo) 18572.4 45,847 8,895 28
4 36968.9 84,313 16,030 52
4 (efifo) 37668.4 85,033 16,100 52
6 61782.0 137,262 23,655 100
6 (efifo) 61848.3 137,722 24,149 100
8 81030.8 178,550 30,919 100
8 (efifo) 82483.5 179,839 30,874 100
10 106158.6 229,421 37,910 121
10 (efifo) 107929.6 231,037 37,389 121
12 (EW=24) 132253.9 285,764 44,909 148
12(efifo) (EW=24) 134456.2 286,507 44,658 148
12 (EW=32) 139663.6 306,466 47,568 196
12 (efifo) (EW=32) 142032.8 307,525 48,073 196
28.125 10 106875.4 229,084 37,796 121
10 (efifo) 107892.5 230,967 38,150 121
12 (EW=24) 133520.9 284,248 44,952 148
12 (efifo) (EW=24) 134528.4 288,160 45,313 148
12 (EW=32) 140658.5 305,778 47,707 196
12 (efifo) (EW=32) 142005.3 308,075 47,802 196
FHT 26.5625 1 (efifo) 18573.8 45,829 8,922 28
2 (efifo) 37665.2 84,939 16,050 52
3 (efifo) 61855.9 137,992 24,016 100
4 (efifo) 82416.8 179,5381 30,857 100
Table 6.  Resource Utilization for Interlaken Look-aside ModeThe following numbers were obtained using the Quartus® Prime Pro Edition software version 23.4
Transceiver Mode PMA Type Data Rate (Gbps) Number of Lanes Resource Utilization
ALMs Logic Registers M20K Blocks
Primary Secondary
NRZ FGT 6.25 4 13658.1 31098 5783 0
10.3125 8 27896.0 55644 10532 0
12 43710.0 82273 15752 0
12.5 4 13655.1 31196 5736 0
8 27857.1 55804 10451 0
10 35247.9 70464 12853 0
12 43705.6 82448 15563 0
25.78125 4 13664.9 31106 6153 0
6 20539.8 43626 8476 0
8 27871.2 55610 11034 0
10 35234.3.8 70757 13356 0
12 43756.9 82810 16251 0
PAM4 FGT 26.5625 2 13392.5 35231 6528 0
2 (efifo) 13613.3 35421 6777 0
4 27308.0 63253 12298 0
4 (efifo) 27874.6 63868 12506 0
6 42403.7 93995 17871 0
6 (efifo) 43255.5 94818 18371 0
FHT 26.5625 1 (efifo) 13603.4 35466 6718 0
2 (efifo) 27871.4 63691 12615 0
3 (efifo) 43210.5 94571 18368 0
Note: EW = user interface width (words)
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