AN 887: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Arria® 10 Devices

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ID 683608
Date 5/24/2019
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Document Table of Contents
Document Table of Contents x
1. PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Arria® 10 Devices
1. PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Arria® 10 Devices x
1.1. Features 1.2. Hardware and Software Requirements 1.3. Design System Architecture Overview 1.4. Dynamic Reconfiguration Overview 1.5. PHY Lite Per-Bit Overview 1.6. Compiling the Reference Design 1.7. Hardware Testing 1.8. Document Revision History for AN 887: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Arria® 10 Devices 1.9. Appendix A: HiLo Loopback Card Pin Connections 1.10. Appendix B: Retrieving Lane and Pin Information 1.11. Appendix C: Decoding Parameter Table
1.3. Design System Architecture Overview x
1.3.1. Functional Description
1.3.1. Functional Description x
1.3.1.1. DUT_MODULE 1.3.1.2. Traffic Generator/Checker Module 1.3.1.3. DYN_CFG Controller 1.3.1.4. Clocking Scheme
1.4. Dynamic Reconfiguration Overview x
1.4.1. Register Address Map 1.4.2. Dynamic Reconfiguration API Functions
1.5. PHY Lite Per-Bit Overview x
1.5.1. Per-Bit Deskew Concept 1.5.2. Read Deskew Algorithm
1.7. Hardware Testing x
1.7.1. Setting Up the Development Kit 1.7.2. Generating Executable and Linking Format (.elf) Programming File 1.7.3. Running the Hardware Reference Design 1.7.4. Results
1.7.4. Results x
1.7.4.1. Dynamic Calibration Result 1.7.4.2. Random Data Transfer Result
1. PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Arria® 10 Devices

1. PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Arria® 10 Devices

The PHY Lite for Parallel Interfaces reference design demonstrates the usage of the dynamic reconfiguration feature using the PHY Lite for Parallel Interfaces Intel® Arria® 10 FPGA IP core.

Two instances of PHY Lite for Parallel Interfaces Intel® Arria® 10 FPGA IP cores are placed in different I/O tiles on a single FPGA. Each PHY Lite instance is configured to have two groups and is loopback using a custom HiLo loopback card on the Intel® Arria® 10 GX FPGA development kit. One PHY Lite instance is configured as a transmitter (DUT_OUTPUT) and the other PHY Lite instance is configured as a receiver (DUT_INPUT).

Figure 1. Block Diagram—PHY Lite for Parallel Interfaces Reference Design System for Intel® Arria® 10 Devices
Note: For the HiLo loopback card pin connections, refer to Appendix A: HiLo Loopback Card Pin Connections. For more information about the HiLo loopback card, contact Intel® Support.

Section Content
Features
Hardware and Software Requirements
Design System Architecture Overview
Dynamic Reconfiguration Overview
PHY Lite Per-Bit Overview
Compiling the Reference Design
Hardware Testing
Document Revision History for AN 887: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel Arria 10 Devices
Appendix A: HiLo Loopback Card Pin Connections
Appendix B: Retrieving Lane and Pin Information
Appendix C: Decoding Parameter Table

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