AN 887: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Arria® 10 Devices

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ID 683608
Date 5/24/2019
Public
Document Table of Contents
Document Table of Contents x
1. PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Arria® 10 Devices
1. PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Arria® 10 Devices x
1.1. Features 1.2. Hardware and Software Requirements 1.3. Design System Architecture Overview 1.4. Dynamic Reconfiguration Overview 1.5. PHY Lite Per-Bit Overview 1.6. Compiling the Reference Design 1.7. Hardware Testing 1.8. Document Revision History for AN 887: PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Arria® 10 Devices 1.9. Appendix A: HiLo Loopback Card Pin Connections 1.10. Appendix B: Retrieving Lane and Pin Information 1.11. Appendix C: Decoding Parameter Table
1.3. Design System Architecture Overview x
1.3.1. Functional Description
1.3.1. Functional Description x
1.3.1.1. DUT_MODULE 1.3.1.2. Traffic Generator/Checker Module 1.3.1.3. DYN_CFG Controller 1.3.1.4. Clocking Scheme
1.4. Dynamic Reconfiguration Overview x
1.4.1. Register Address Map 1.4.2. Dynamic Reconfiguration API Functions
1.5. PHY Lite Per-Bit Overview x
1.5.1. Per-Bit Deskew Concept 1.5.2. Read Deskew Algorithm
1.7. Hardware Testing x
1.7.1. Setting Up the Development Kit 1.7.2. Generating Executable and Linking Format (.elf) Programming File 1.7.3. Running the Hardware Reference Design 1.7.4. Results
1.7.4. Results x
1.7.4.1. Dynamic Calibration Result 1.7.4.2. Random Data Transfer Result
1. PHY Lite for Parallel Interfaces Reference Design with Dynamic Reconfiguration for Intel® Arria® 10 Devices

1.11. Appendix C: Decoding Parameter Table

Figure 27. Parameter Table Example for Intel® Arria® 10 Devices
Notes to Figure 27:
  1. To access the parameter table = 24’hE000
  2. To determine the size of the parameter table, generate an address. For example: 
    addr = 24’hE000 + 24’h14
value at addr = 0xA4

    The size of parameter table is AC, which means that information about the PHY Lite for Parallel Interfaces IP cores are spread from address 27’hE000 to 27’hE0A4.

  3. To determine the address offset of the PHY Lite for Parallel Interfaces IP cores in the parameter table.
    • There are two PHY Lite for Parallel Interfaces IP cores in the parameter table at address offset. For example: 
      27’hE018 = 84000044
27’hE01C = 85000074

      where 0x44 address offset points to PHY Lite for Parallel Interfaces IP core 1 and 0x74 address offset points to PHY Lite for Parallel Interfaces IP core 2.

    • 4 and 5 (marked in yellow box) are the PHY Lite for Parallel Interfaces IP core interface IDs.
  4. To determine the number of groups in the first PHY Lite for Parallel Interfaces IP core interface: 
    24’hE048 = 00000002

    The underlined number indicates that there is only two groups.

  5. To determine the group information (for example, the number of lanes and pins in a PHY Lite for Parallel Interfaces IP core interface per group): 
    24’hE04C = 00000606
    where
    • num_lanes[7:6],num_pins[5:0] means lanes = 1 and pins = 6 of Group 0.
    • and num_lanes[7:6],num_pins[5:0] means lanes = 1 and pins = 6 of Group 1.
  6. To determine the lane and pin address offsets of each group: 
    24’hE054 = 00590068
    where lane_off[31:16],pin_off[15:0] means
    • lane off = 0x58 and pin off = 0x5C of Group 0.
    • lane off = 0x59 and pin off = 0x68 of Group 1.
  7. To determine the lane address of each group: 
    24’hE058 =   00003930
    where
    • Lane address of Group 0 = 0x30
    • Lane address of Group 1 = 0x39
  8. To determine the pin address at 24’hE05C to 24’hE064 for Group 0: 
    24’hE05C = 30E530E4 (for Group 0)
    where
    • DQS_P = Pin 4; DQS_N = Pin 5
    • DQ[0] = Pin 6; DQ[1] = Pin 7
    • DQ[2] = Pin 0; DQ[3] = Pin 1
    24’hE068 = 39E539E4 (for Group 1)
    where
    • DQS_P = Pin 4; DQS_N = Pin 5
    • DQ[4] = Pin 9; DQ[5] = Pin 6
    • DQ[6] = Pin 3; DQ[7] = Pin 8
    Note: {lane_addr[7:0],0xE,pin[3:0]} for strobe and {lane_addr[7:0],0xF,pin[3:0]} for data.
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