DisplayPort Intel® Cyclone 10 GX FPGA IP Design Example User Guide
ID
683603
Date
9/02/2022
Public
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2.1. Intel® Cyclone® 10 GX DisplayPort SST Parallel Loopback Design Features
2.2. Intel® Cyclone® 10 GX DisplayPort MST Parallel Loopback Design Features
2.3. Intel® Cyclone® 10 GX DisplayPort SST TX-only or RX-only Design Features
2.4. Enabling Adaptive Sync Support
2.5. Design Components
2.6. Clocking Scheme
2.7. Interface Signals and Parameter
2.8. Hardware Setup
2.9. Simulation Testbench
2.10. DisplayPort Transceiver Reconfiguration Flow
2.11. Transceiver Lane Configurations
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
| Updated for: |
|---|
| Intel® Quartus® Prime Design Suite 22.2 |
| IP Version 21.0.1 |
The DisplayPort Intel® FPGA IP design examples for Intel® Cyclone® 10 GX devices feature a simulating testbench and a hardware design that supports compilation and hardware testing.
The DisplayPort Intel® FPGA IP offers the following design examples:
- DisplayPort SST TX-only
- DisplayPort SST RX-only
- DisplayPort SST parallel loopback with a Pixel Clock Recovery (PCR) module
- DisplayPort SST parallel loopback without a PCR module
- DisplayPort MST parallel loopback with a PCR module
- DisplayPort MST parallel loopback without a PCR module
When you generate a design example, the parameter editor automatically creates the files necessary to simulate, compile, and test the design in hardware.
Figure 1. Development Steps