Intel® Stratix® 10 SEU Mitigation User Guide

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ID 683602
Date 2/20/2024
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 SEU Mitigation Overview 2. Intel® Stratix® 10 Mitigation Techniques for CRAM 3. Secure Device Manager ECC Error Detection 4. Intel® Stratix® 10 SEU Mitigation Implementation Guides 5. Advanced SEU Detection Intel® FPGA IP References 6. Intel® Stratix® 10 Fault Injection Debugger References 7. Intel® Stratix® 10 SEU Mitigation User Guide Archives 8. Document Revision History for the Intel® Stratix® 10 SEU Mitigation User Guide
1. Intel® Stratix® 10 SEU Mitigation Overview x
1.1. SEU Mitigation Techniques for Intel® Stratix® 10 Devices 1.2. Configuration RAM 1.3. Memory Blocks Error Correction Code (ECC) Support 1.4. Secure Device Manager ECC Error 1.5. Triple-Module Redundancy 1.6. Failure Rates
2. Intel® Stratix® 10 Mitigation Techniques for CRAM x
2.1. CRAM Error Detection and Correction 2.2. Internal Scrubbing and Priority Scrubbing 2.3. SEU Sensitivity Processing 2.4. Designating the Sensitivity of the Design Hierarchy 2.5. Evaluating a System's Response to Functional Upsets
2.1. CRAM Error Detection and Correction x
2.1.1. Error Message Queue 2.1.2. SEU_ERROR Pin Behavior
2.2. Internal Scrubbing and Priority Scrubbing x
2.2.1. Internal Scrubbing 2.2.2. Priority Scrubbing
2.3. SEU Sensitivity Processing x
2.3.1. Advanced SEU Detection IP Core
2.3.1. Advanced SEU Detection IP Core x
2.3.1.1. Release Information for Advanced SEU Detection Intel® FPGA IP 2.3.1.2. On-Chip Lookup Sensitivity Processing 2.3.1.3. Off-Chip Lookup Sensitivity Processing 2.3.1.4. SMH Lookup
2.3.1.3. Off-Chip Lookup Sensitivity Processing x
2.3.1.3.1. Off-Chip Lookup Sensitivity Processing Operation Flow
2.3.1.4. SMH Lookup x
2.3.1.4.1. SMH Revision 4 File Format
2.4. Designating the Sensitivity of the Design Hierarchy x
2.4.1. Hierarchy Tagging
2.5. Evaluating a System's Response to Functional Upsets x
2.5.1. Intel® Quartus® Prime Fault Injection Debugger
3. Secure Device Manager ECC Error Detection x
3.1. SDM ECC Error Message Bits 3.2. SDM ECC Error Signals Behavior
4. Intel® Stratix® 10 SEU Mitigation Implementation Guides x
4.1. Setting SEU_ERROR Pin 4.2. Intel® Quartus® Prime SEU Software Settings 4.3. Enabling Priority Scrubbing 4.4. Performing Hierarchy Tagging 4.5. Programming Sensitivity Map Header File into Memory 4.6. Performing Lookup for Sensitivity Map Header 4.7. Using the Fault Injection Debugger 4.8. Analyzing SEU Errors Using Signal Tap 4.9. Intel® Quartus® Prime Software SEU FIT Reports
4.7. Using the Fault Injection Debugger x
4.7.1. Enabling the Fault Injection Debugger 4.7.2. Launching and Setting Up the Fault Injection Debugger 4.7.3. Configuring Your Device and the Fault Injection Debugger 4.7.4. Constraining Regions for Fault Injection 4.7.5. Injecting Errors 4.7.6. Injecting Double Adjacent Errors
4.7.5. Injecting Errors x
4.7.5.1. Injecting Errors to a Random Location 4.7.5.2. Injecting Errors to a Specific Location
4.7.6. Injecting Double Adjacent Errors x
4.7.6.1. Injecting Double Adjacent Errors: Command-Line Interface 4.7.6.2. Injecting Double Adjacent Errors: GUI with Tcl Console
4.9. Intel® Quartus® Prime Software SEU FIT Reports x
4.9.1. Enabling the Projected SEU FIT by Component Usage Report 4.9.2. SEU FIT Parameters Report 4.9.3. Projected SEU FIT by Component Usage Report
4.9.3. Projected SEU FIT by Component Usage Report x
4.9.3.1. Component FIT Rates 4.9.3.2. Raw FIT 4.9.3.3. Utilized FIT 4.9.3.4. Mitigated FIT 4.9.3.5. Architectural Vulnerability Factor
4.9.3.3. Utilized FIT x
4.9.3.3.1. Comparing .smh Critical Bits Report to Utilized Bit Count 4.9.3.3.2. Considerations for Small Designs
5. Advanced SEU Detection Intel® FPGA IP References x
5.1. Advanced SEU Detection Intel® FPGA IP Parameter Settings 5.2. Advanced SEU Detection Intel® FPGA IP Ports
6. Intel® Stratix® 10 Fault Injection Debugger References x
6.1. Fault Injection Debugger Interface Parameters 6.2. Fault Injection Debugger Command-Line Interface
1. Intel® Stratix® 10 SEU Mitigation Overview
2. Intel® Stratix® 10 Mitigation Techniques for CRAM
3. Secure Device Manager ECC Error Detection
4. Intel® Stratix® 10 SEU Mitigation Implementation Guides
5. Advanced SEU Detection Intel® FPGA IP References
6. Intel® Stratix® 10 Fault Injection Debugger References
7. Intel® Stratix® 10 SEU Mitigation User Guide Archives
8. Document Revision History for the Intel® Stratix® 10 SEU Mitigation User Guide

2.2.2. Priority Scrubbing

You can assign portions of the design as high priority sectors for internal scrubbing; the unassigned portions become low priority sectors. The Intel® Stratix® 10 EDC circuitry detects and corrects errors that occur in the high priority sectors more frequently than the other sectors.

The EDC operation for the priority sectors and non-priority sectors run in parallel when priority scrubbing is enabled. The sectors in group 0 of both the priority sectors and non-priority sectors run the EDC process at time T0. This is followed by the EDC operation of sectors in group 1 of both the priority sectors and non-priority sectors at time T1, sectors in group 2 at time T2, followed by the sectors of the remaining group until the last available group. This corresponds to 1 complete cycle of the EDC process.

For an Intel® Stratix® 10 device with a total of 25 sectors and the maximum number of sectors allowed to run EDC concurrently, Smax = 2, Intel® Quartus® Prime will determine the number of groups for the priority sectors, GP and non-priority sectors, GN based on the number of priority sectors, P and non-priority sectors, N. Within GP, there is at most Smax-1 number of sectors allocated so that there is at least one sector slot left for the normal sector to run concurrently.

If P≤Smax-1, then GP = 1 and GN is determined by allocating N to the vacant sector slots. For example, P+N = 25, where P = 1 and N = 24, as shown on the left side of the following figure. Since P≤Smax-1, then GP = 1. One sector is occupied by the priority sectors and another sector slot is occupied by the non-priority sectors. GN = 24, is determined by allocating N into one sector slot. The priority sectors only need one unit of time to complete the EDC process compared to the non-priority sectors which need 24 units of time.

If P>Smax-1, then GP and GN are determined by allocating P equally into Smax-1 and N to the last vacant sector slot. For example, P = 4 and N = 21 as shown on the right side of the following figure. Since P>Smax-1, then GP = 4 where the priority sectors are divided equally. One sector slot is occupied by the priority sectors and another sector slot is occupied by the non-priority sectors, resulting in GN = 21. The priority sectors only need four units of time to complete the EDC process compared to the non-priority sectors which need 21 units of time.

With priority scrubbing, priority sectors will undergo more frequent SEU detection and correction compared to non-priority scrubbing. This provides faster SEU detection and correction for critical design modules. The interval time for priority sectors is always the minimum interval that the Intel® Stratix® 10 device is capable of, regardless of the user setting of the Minimum SEU Interval in Device and Pin Options. For example, the interval time for one priority sectors is always 1800 microseconds regardless if the Minimum SEU Interval is set to 0 or 10000 microseconds.

A warning message is prompted in Intel® Quartus® Prime when P exceeds a certain threshold which causes the priority sectors to require a longer time to complete one cycle of EDC process compared to the non-priority sectors.

Priority Scrubbing
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