Stratix® 10 SEU Mitigation User Guide

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ID 683602
Date 10/10/2025
Public
Document Table of Contents
Document Table of Contents x
1. Stratix® 10 SEU Mitigation Overview 2. Stratix® 10 Mitigation Techniques for CRAM 3. Secure Device Manager ECC Detection 4. Stratix® 10 SEU Mitigation Implementation Guides 5. Advanced SEU Detection IP References 6. Stratix® 10 Fault Injection Debugger References 7. Stratix® 10 SEU Mitigation User Guide Archives 8. Document Revision History for the Stratix® 10 SEU Mitigation User Guide
1. Stratix® 10 SEU Mitigation Overview x
1.1. SEU Mitigation Techniques for Stratix® 10 Devices 1.2. Configuration RAM 1.3. Memory Blocks Error Correction Code (ECC) Support 1.4. Secure Device Manager ECC Error 1.5. Triple-Module Redundancy 1.6. Failure Rates
2. Stratix® 10 Mitigation Techniques for CRAM x
2.1. CRAM Error Detection and Correction 2.2. Internal Scrubbing and Priority Scrubbing 2.3. SEU Sensitivity Processing 2.4. Designating the Sensitivity of the Design Hierarchy 2.5. Evaluating a System's Response to Functional Upsets
2.1. CRAM Error Detection and Correction x
2.1.1. Error Message Queue 2.1.2. SEU_ERROR Pin Behavior
2.2. Internal Scrubbing and Priority Scrubbing x
2.2.1. Internal Scrubbing 2.2.2. Priority Scrubbing
2.3. SEU Sensitivity Processing x
2.3.1. Advanced SEU Detection IP
2.3.1. Advanced SEU Detection IP x
2.3.1.1. Release Information for Advanced SEU Detection IP 2.3.1.2. On-Chip Lookup Sensitivity Processing 2.3.1.3. Off-Chip Lookup Sensitivity Processing 2.3.1.4. SMH Lookup
2.3.1.3. Off-Chip Lookup Sensitivity Processing x
2.3.1.3.1. Off-Chip Lookup Sensitivity Processing Operation Flow
2.3.1.4. SMH Lookup x
2.3.1.4.1. SMH Revision 4 File Format
2.4. Designating the Sensitivity of the Design Hierarchy x
2.4.1. Hierarchy Tagging
2.5. Evaluating a System's Response to Functional Upsets x
2.5.1. Quartus® Prime Fault Injection Debugger
3. Secure Device Manager ECC Detection x
3.1. SDM ECC Error Message Bits 3.2. SDM ECC Error Signals Behavior
4. Stratix® 10 SEU Mitigation Implementation Guides x
4.1. Setting the SEU_ERROR Pin 4.2. Setting Up the SEU Mitigation Features 4.3. Enabling Priority Scrubbing 4.4. Performing Hierarchy Tagging 4.5. Programming Sensitivity Map Header File into Memory 4.6. Performing Lookup for Sensitivity Map Header 4.7. Using the Fault Injection Debugger 4.8. Analyzing SEU Errors Using Signal Tap 4.9. Quartus® Prime Software SEU FIT Reports
4.7. Using the Fault Injection Debugger x
4.7.1. Enabling the Fault Injection Debugger 4.7.2. Launching and Setting Up the Fault Injection Debugger 4.7.3. Configuring Your Device and the Fault Injection Debugger 4.7.4. Constraining Regions for Fault Injection 4.7.5. Injecting Errors 4.7.6. Injecting Double Adjacent Errors
4.7.5. Injecting Errors x
4.7.5.1. Injecting Errors to a Random Location 4.7.5.2. Injecting Errors to a Specific Location
4.7.6. Injecting Double Adjacent Errors x
4.7.6.1. Injecting Double Adjacent Errors: Command-Line Interface 4.7.6.2. Injecting Double Adjacent Errors: GUI with Tcl Console
4.9. Quartus® Prime Software SEU FIT Reports x
4.9.1. Enabling the Projected SEU FIT by Component Usage Report 4.9.2. SEU FIT Parameters Report 4.9.3. Projected SEU FIT by Component Usage Report
4.9.3. Projected SEU FIT by Component Usage Report x
4.9.3.1. Component FIT Rates 4.9.3.2. Raw FIT 4.9.3.3. Utilized FIT 4.9.3.4. Mitigated FIT 4.9.3.5. Architectural Vulnerability Factor
4.9.3.3. Utilized FIT x
4.9.3.3.1. Comparing .smh Critical Bits Report to Utilized Bit Count 4.9.3.3.2. Considerations for Small Designs
5. Advanced SEU Detection IP References x
5.1. Advanced SEU Detection IP Parameter Settings 5.2. Advanced SEU Detection IP Ports
6. Stratix® 10 Fault Injection Debugger References x
6.1. Fault Injection Debugger Interface Parameters 6.2. Fault Injection Debugger Command-Line Interface
1. Stratix® 10 SEU Mitigation Overview
2. Stratix® 10 Mitigation Techniques for CRAM
3. Secure Device Manager ECC Detection
4. Stratix® 10 SEU Mitigation Implementation Guides
5. Advanced SEU Detection IP References
6. Stratix® 10 Fault Injection Debugger References
7. Stratix® 10 SEU Mitigation User Guide Archives
8. Document Revision History for the Stratix® 10 SEU Mitigation User Guide

2.5.1. Quartus® Prime Fault Injection Debugger

You can detect and debug single event upset (SEU) using the Fault Injection Debugger in the Quartus® Prime software. Use the debugger to inject errors into the configuration RAM (CRAM) of an Stratix® 10 FPGA device.

With the Fault Injection Debugger, you can operate the FPGA in the system and inject random CRAM bit flips. These simulated SEU strikes allow you to observe how the FPGA and the system detect and recover from SEUs. Depending on the results, you can refine the system's recovery sequence.

Figure 7.  Fault Injection Debugger Overview Block Diagram for Stratix® 10 Devices

The Fault Injection Debugger allows you to perform the following:

  • Inject single-bit error to either:
    • Random location
    • Specified region
  • Report error information by reading the error message queue
Note: The Fault Injection Debugger does not support injecting SDM ECC error in Stratix® 10 devices.
Note: To use the Fault Injection Debugger, you require a licensed Quartus® Prime software with the "fault_injection_debugger_tool" feature (Fault Injection(D028)) in the license. To check if you have the feature in your license, from the Quartus® Prime software menu, select Assignment > Device. Click Device and Pin Options and then navigate to Error Detection CRC. If you can turn on Allow SEU fault injection, then you have the necessary license to use the Fault Injection Debugger tool.
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