1. Intel® Stratix® 10 SEU Mitigation Overview
2. Intel® Stratix® 10 Mitigation Techniques for CRAM
3. Secure Device Manager ECC Error Detection
4. Intel® Stratix® 10 SEU Mitigation Implementation Guides
5. Advanced SEU Detection Intel® FPGA IP References
6. Intel® Stratix® 10 Fault Injection Debugger References
7. Intel® Stratix® 10 SEU Mitigation User Guide Archives
8. Document Revision History for the Intel® Stratix® 10 SEU Mitigation User Guide
4.1. Setting SEU_ERROR Pin
4.2. Intel® Quartus® Prime SEU Software Settings
4.3. Enabling Priority Scrubbing
4.4. Performing Hierarchy Tagging
4.5. Programming Sensitivity Map Header File into Memory
4.6. Performing Lookup for Sensitivity Map Header
4.7. Using the Fault Injection Debugger
4.8. Analyzing SEU Errors Using Signal Tap
4.9. Intel® Quartus® Prime Software SEU FIT Reports
2.1.1. Error Message Queue
The Intel® Stratix® 10 device error message queue stores the error messages when detecting an SEU error. Each error message contains information about the sector address, error type, and error location. The error message queue is capable of storing a maximum of eight different messages. A warning message appears if the error message queue has more than eight different messages. Click Read EMR to display and clear the error message queue.
You can retrieve the contents of the error message queue using the following tools:
- Fault Injection Debugger tool
- Advanced SEU Detection Intel® FPGA IP
- Mailbox command
Note: Do not use this mailbox command if your design contains the Advanced SEU Detection Intel® FPGA IP.
You may send the mailbox command via JTAG interface using Configuration Debugger Tool to retrieve the SEU error message:
- From the Intel® Quartus® Prime menu, select Tools > Configuration Debugger.
- Select the hardware in Hardware Setup and click Load Device to select your device.
- Click View and select SDM Tool to enable the Mailbox Client window.
- Specify the Command Code and Parameter List.
- Click Send and read the response in Session Log.
Figure 2. Executing the read_seu_error Mailbox Command via JTAG Interface Using the Configuration Debugger ToolThe figure below shows a corrected error at sector 77 in frame 9B1 and bit 594.
Name | Width | Bit | Description |
---|---|---|---|
Sector address (Most significant 32-bit word in avst_seu_source_data signal |
32 | 31:24 | Reserved |
23:16 | Address of sector with error | ||
15:8 | Reserved | ||
7:4 | Error type:
|
||
3:0 | Reserved | ||
Error location2 (Least significant 32-bit word in avst_seu_source_data signal) |
32 | 31:29 | Bit 31:29—Error type:
|
28 | Correction Status:
|
||
27:24 | Reserved | ||
23:12 | Bit position within frame | ||
11:0 | Combined of Row and Frame index |
Note: Intel® recommends that you turn on the Internal Scrubbing feature. If an error is detected in a sector, and you did not enable the Internal Scrubbing option, the SEU feature for that particular sector is turned off. Additionally, subsequent SEU occurrence in the same sector either correctable or uncorrectable error, is not detected.
Related Information
2 For single bit error with internal scrubbing, the error location provides the error bit position. For multiple bits error or single bit error without internal scrubbing, bit [23:0] returns 0.