CPRI IP User Guide

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ID 683595
Date 6/13/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the CPRI IP 2. Getting Started with the CPRI IP 3. CPRI IP Functional Description 4. CPRI IP Signals 5. CPRI IP Registers 6. CPRI Altera® FPGA IP User Guide Archives 7. Document Revision History for the CPRI IP User Guide
1. About the CPRI IP x
1.1. CPRI IP Features 1.2. CPRI IP Device Family and Speed Grade Support 1.3. IP Verification 1.4. Resource Utilization for CPRI IP 1.5. CPRI IP Release Information
1.2. CPRI IP Device Family and Speed Grade Support x
1.2.1. CPRI IP Device Family Support 1.2.2. CPRI IP Device and Transceiver Speed Grade Support
2. Getting Started with the CPRI IP x
2.1. Installation and Licensing 2.2. Generating a CPRI IP 2.3. CPRI IP Parameters 2.4. Integrating the CPRI IP into your Design: Required External Blocks 2.5. Simulating Intel FPGA IP Cores 2.6. Running the CPRI IP Design Example 2.7. CPRI IP Design Example Clocks 2.8. About the Testbench 2.9. Compiling the Full Design and Programming the FPGA
2.1. Installation and Licensing x
2.1.1. Intel FPGA IP Evaluation Mode
2.2. Generating a CPRI IP x
2.2.1. CPRI IP Generated Files
2.4. Integrating the CPRI IP into your Design: Required External Blocks x
2.4.1. Adding the Transceiver TX PLL IP 2.4.2. Adding the Reset Controller 2.4.3. Adding the Transceiver Reconfiguration Controller 2.4.4. Adding the Off-Chip Clean-Up PLL 2.4.5. Adding and Connecting the Single-Trip Delay Calibration Blocks 2.4.6. CPRI IP Transceiver PLL Calibration 2.4.7. Reference and System PLL Clock for your IP Design
2.4.7. Reference and System PLL Clock for your IP Design x
2.4.7.1. System PLL Connections for the Agilex® 7 F-tile Variations 2.4.7.2. System PLL Connections for the Agilex 5 Variations 2.4.7.3. Reset Sequencer Connections for the Agilex 5 Variations
3. CPRI IP Functional Description x
3.1. Interfaces Overview 3.2. CPRI IP Clocking Structure 3.3. CPRI IP Reset Requirements 3.4. Start-Up Sequence Following Reset 3.5. AUX Interface 3.6. Direct IQ Interface 3.7. Ctrl_AxC Interface 3.8. Direct Vendor Specific Access Interface 3.9. Real-Time Vendor Specific Interface 3.10. Direct HDLC Serial Interface 3.11. Direct L1 Control and Status Interface 3.12. L1 Debug Interface 3.13. Media Independent Interface (MII) to External Ethernet Block 3.14. Gigabit Media Independent Interface (GMII) to External Ethernet Block 3.15. CPU Interface to CPRI IP Registers 3.16. Auto-Rate Negotiation 3.17. Extended Delay Measurement 3.18. CPRI IP Deterministic Latency 3.19. CPRI IP Transceiver and Transceiver Management Interfaces 3.20. Testing Features
3.2. CPRI IP Clocking Structure x
3.2.1. Example CPRI IP Clock Connections in Different Clocking Modes
3.4. Start-Up Sequence Following Reset x
3.4.1. Start-Up Sequence Interface Signals
3.5. AUX Interface x
3.5.1. AUX Interface Signals 3.5.2. AUX Interface Synchronization 3.5.3. Auxiliary Latency Cycles 3.5.4. Direct Interface CPRI Frame Data Format
3.14. Gigabit Media Independent Interface (GMII) to External Ethernet Block x
3.14.1. GMII Normal Mode 3.14.2. Ethernet PCS Bypass Mode 3.14.3. Ethernet PCS Run-Time Switching
3.15. CPU Interface to CPRI IP Registers x
3.15.1. CPU Interface Signals 3.15.2. Accessing the Hyperframe Control Words
3.15.2. Accessing the Hyperframe Control Words x
3.15.2.1. Specifying the Control Word 3.15.2.2. Specifying the Position in the Control Word 3.15.2.3. Retrieving the Hyperframe Control Words 3.15.2.4. Writing the Hyperframe Control Words
3.17. Extended Delay Measurement x
3.17.1. Extended Delay Measurement for Soft Internal Buffers 3.17.2. Extended Delay Measurement for Stratix® 10 Hard FIFOs 3.17.3. Extended Delay Measurement Interface
3.19. CPRI IP Transceiver and Transceiver Management Interfaces x
3.19.1. CPRI Link 3.19.2. Main Transceiver Clock and Reset Signals 3.19.3. Arria V, Arria V GZ, Cyclone V, and Stratix V Transceiver Reconfiguration Interface 3.19.4. Arria® 10, Stratix® 10, and Agilex® 7 Transceiver Reconfiguration Interface 3.19.5. RS-FEC Interface 3.19.6. Interface to the External Reset Controller 3.19.7. Interface to the External PLL 3.19.8. Transceiver Debug Interface
3.20. Testing Features x
3.20.1. CPRI IP Loopback Modes 3.20.2. CPRI IP Self-Synchronization Feature
4. CPRI IP Signals x
4.1. CPRI IP Core L2 Interface 4.2. CPRI IP Core L1 Direct Access Interfaces 4.3. CPRI IP Core Management Interfaces 4.4. CPRI IP Core Transceiver and Transceiver Management Signals
1. About the CPRI IP
2. Getting Started with the CPRI IP
3. CPRI IP Functional Description
4. CPRI IP Signals
5. CPRI IP Registers
6. CPRI Altera® FPGA IP User Guide Archives
7. Document Revision History for the CPRI IP User Guide

3.11. Direct L1 Control and Status Interface

If you turn on Enable direct Z.130.0 alarm bits access interface in the CPRI parameter editor, the direct L1 control and status interface is available. This interface provides direct access to the Z.130.0 alarm and reset signals (loss of frame (LOF), loss of signal (LOS), service access point (SAP) defect indication (SDI), remote alarm indication (RAI), and reset request or acknowledge) in the CPRI hyperframe.

If you connect the AUX interface of your RE target IP to a network switch or other routing layer rather than directly to the downstream RE host, or if you do not fully connect the AUX interface to the downstream RE host, you can use this Z.130.0 access interface to streamline the transfer of reset requests and SDI alarms across hops.

This interface has higher transmit priority than access through the CPRI IP registers.

This interface has the following types of signals:
  • _local_ signals are output signals from the IP about the state of this IP, and also indicate the IP asserts the relevant outgoing Z.130.0 bit in the next CPRI hyperframe according to the transmit priority of this interface.
  • _assert signals are input signals the application can use to request that the IP assert the relevant outgoing Z.130.0 bit in the next CPRI hyperframe according to the transmit priority of this interface. You can also connect these signals in an RE host to the corresponding _req output signals of the upstream RE target in a multi-hop configuration, to support efficient transfer of reset requests and SDI alarms to the IP.
  • _remote signals are output signals from the IP that indicate the IP cre received a Z.130.0 byte on the CPRI link with the relevant bit asserted by the CPRI link partner.
  • _req signals are also output signals from the IP that indicate the IP received a Z.130.0 byte on the CPRI link with the relevant bit asserted by the CPRI link partner. However, these signals are intended to be passed downstream in a multi-hop configuration. If the IP is an RE target, and it connects to an RE host through the Z.130.0 alarm and reset interface in a multi-hop configuration, you can connect the RE target IP _req output signal directly to the corresponding _assert input signal on the downstream RE host for efficient communication of the reset request or SDI alarm.
Table 30.  Direct L1 Control and Status Interface Signals

All interface signals are clocked by the cpri_clkout clock.

Signal Name

Direction

Description

z130_local_lof Output Indicates the IP detects a local loss of frame. In this case, the state_l1_synch output signal indicates the L1 synchronization state machine is in state XACQ1 or XACQ2.

In this case the IP also asserts the local_lof bit in the FLSAR register at offset 0x2C.

z130_local_los Output Indicates the IP detects a local loss of signal. The IP core asserts this flag if it detects excessive 8B/10B errors that trigger the assertion of the optional L1 debug rx_lcv output signal or the xcvr_los output signal and the rx_los field of the L1_CONFIG register.

In this case the IP also asserts the local_los bit in the FLSAR register at offset 0x2C.

z130_sdi_assert Input Indicates that the host service access point (SAP) is not available. Possible causes for this situation are equipment error or that the connected target IP is forwarding an SDI request it detected to the current RE CPRI host IP through a direct connection.
z130_local_rai Output Indicates that either the z130_local_lof or the z130_local_los signal is high; clears when both of those two signals are low. Logical OR of two output signals z130_local_lof and z130_local_los.

z130_reset_assert Input Reset request from the application or from an RE target to the current RE CPRI host IP through a direct connection.
z130_remote_lof Output Indicates LOF received in Z.130.0 control byte from remote CPRI link partner.

In this case the IP also asserts the remote_lof bit in the FLSAR register at offset 0x2C.

z130_remote_los Output Indicates LOS received in Z.130.0 control byte from remote CPRI link partner.

In this case the IP also asserts the remote_los bit in the FLSAR register at offset 0x2C.

z130_sdi_req Output Indicates remote SAP defect indication received in Z.130.0 control byte from remote CPRI link host. If the current CPRI IP is an RE target in a multi-hop configuration, you should connect this output signal directly to the z130_sdi_assert input signal of the downstream RE host.
z130_remote_rai Output Asserts when either z130_remote_lof or z130_remote_los is asserted, and clears when both z130_remote_lof and z130_remote_los have the value of 0.

In this case the IP also asserts the rai_detected bit in the FLSAR register at offset 0x2C.

z130_reset_req Output If the current IP is a CPRI link target, indicates the IP core received a reset request in the Z.130.0 control byte from the remote CPRI link host.

If the current IP is a CPRI link host, indicates the IP received a reset acknowledgement in the Z.130.0 control byte from the remote CPRI link target.

Figure 50. sdi_assert to sdi_req on Direct L1 Control and Status Interface


Figure 51. reset_assert to reset_req on Direct L1 Control and Status Interface


Figure 52. LOF, LOS, and RAI on Direct L1 Control and Status Interface


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