Intel® FPGA Temperature Sensor IP Core User Guide

ID 683585
Date 5/30/2018
Public

Compiling the Intel® FPGA Temperature Sensor IP Core Example Design

To compile the Intel® FPGA Temperature Sensor IP core in the Intel® Quartus® Prime software, follow these steps:
  1. Open the top-level file alttemp_sense_ex1.bdf in the Intel® Quartus® Prime Block Editor software. This file contains the input and output assignments and a placeholder for the tsd_s4 module.
  2. To insert the tsd_s4 module, double-click on the Block Editor window. The Symbol window appears.
  3. Under Name, browse to the tsd_s4.bsf file.
  4. Click OK.
  5. Place the tsd_s4 module onto the INSERT TSD_S4 BLOCK HERE placeholder so that the module aligns with the input and output ports.
    Figure 3. Complete Design FileThis figure shows the complete design file.
  6. On the Processing menu, click Start Compilation.
  7. When the Full Compilation was successful message box appears, click OK.