Triple-Speed Ethernet Stratix® 10 FPGA IP Design Example User Guide

ID 683551
Date 9/29/2025
Public
Document Table of Contents

1.2.5. Hardware Testing

You can compile and test the design using the supported Altera FPGA development kit.

In the Clock Controller application, which is part of the development kit, set the following frequencies:

  • Si5341A: OUT5—156.25 MHz