H-Tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP Core Release Notes

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Date 6/22/2020
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1. Intel® Stratix® 10 H-Tile Hard IP for Ethernet IP Core Release Notes
1. Intel® Stratix® 10 H-Tile Hard IP for Ethernet IP Core Release Notes x
1.1. H-Tile Hard IP for Ethernet Intel Stratix 10 FPGA IP Core v20.2 1.2. H-Tile Hard IP for Ethernet Intel Stratix 10 FPGA IP Core v18.0 1.3. Intel® Stratix® 10 H-Tile Hard IP for Ethernet IP Core v17.1
1. Intel® Stratix® 10 H-Tile Hard IP for Ethernet IP Core Release Notes

1.2. H-Tile Hard IP for Ethernet Intel Stratix 10 FPGA IP Core v18.0

Table 2.  Version 18.0 May 2018
Description Impact Notes

Added support for Optical Transport Network (OTN) and Flexible Ethernet.

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Added deficit idle counter (DIC) option for more refined inter-packet gap (IPG) control.

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Added the following GUI parameters:
  • Link fault generation option
  • Enable asynchronous adapter clock
  • Enable Altera Debug Master Endpoint (ADME)
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Added simulation design examples for:
  • 50GE and 100GE OTN variation
  • 50GE and 10GE FlexE variation
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Added hardware design example for 50GE and 100GE MAC + PCS variant.

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