R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683544
Date 4/12/2024
Public

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2.4.5.9. BFM Configuration Procedures

The BFM configuration procedures are available in altpcietb_bfm_rp_gen5_x16.sv. These procedures support configuration of the Root Port and Endpoint Configuration Space registers.

All Verilog HDL arguments are type integer and are input‑only unless specified otherwise.