R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683544
Date 3/28/2022

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Document Table of Contents

1.1. Credit Initialization Sequence

In R-tile, the back-pressure mechanism by the PIO component is done through the credit system. Therefore, the credit value must be declared during the credit initialization stage. An initial TX credit value is captured by the DUT and will be deducted for any TLP sent to the PIO. When the credit value reaches zero, the DUT stops sending any more TLP until the credit is returned by the PIO.

For the R-tile design example, the RX_CRDT_INIT block interfaces with the credit signals from the DUT as shown in the figure below. The block focuses on initializing and returning the RX credit. In the TX direction, only crdt_init_ack is asserted in the block to complete the initialization stage. The PIO component will capture the TX credit during the initialization stage, which is initiated by the DUT.

Figure 6. Credit System of the Design Example

The waveforms below show the initialization sequence for RX credit from PIO to DUT. During the initialization phase, the *crdt_init signal is asserted by the PIO. In response, the DUT will assert the *crdt_init_ack. After receiving the ack signal, the *crdt_update is asserted and the *crdt_update_cnt value is captured by the internal crdt_cnt by the DUT

Figure 7. Waveforms of Credit Transactions During the Initialization Stage