Intel® FPGA SDK for OpenCL™ Pro Edition: Best Practices Guide

ID 683521
Date 10/04/2021
Public

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2.4.2. Features of the Kernel Memory Viewer

Data movement is a bottleneck in many algorithms. The Kernel Memory Viewer in the High Level Design Report (report.html) shows you how the Intel® FPGA SDK for OpenCL™ Offline Compiler interprets the data connections and synthesizes memory for your kernel. Use the Kernel Memory Viewer to help you identify data movement bottlenecks in your kernel design.

Some patterns in memory accesses can cause undesired arbitration in the load-store units (LSUs), which can affect the throughput performance of your kernel. Use the Kernel Memory Viewer to identify unwanted arbitration in the LSUs.

Access the Kernel Memory Viewer by clicking System Viewers > Kernel Memory Viewer.

The following image illustrates the layout of the Kernel Memory Viewer:

Figure 19. Kernel Memory Viewer Layout

The Kernel Memory Viewer has the following panes:

Kernel Memory List
Lists all memories present in your design. When you select a memory name, you can view its graphical representation in the Kernel Memory Viewer pane.
Kernel Memory Viewer
Shows a graphical representation of the memory system or memory bank selected in the Kernel Memory List pane.
Code View
Shows the source code file for which the reports are generated.
Details
Shows the details of the memory system or memory bank selected in the Kernel Memory List pane.

Kernel Memory List

The Kernel Memory List pane displays a hierarchy of kernels with memories synthesized (RAMs, ROMs, and registers) and optimized away in that kernel.

Figure 20. Features and Details of the Kernel Memory List Pane

The following table describes each numbered feature highlighted in the above image:

Table 1.  Kernel Memory List Pane Icons and Labels
  Icon or Label Name Description
1 Kernel name The list of memories in your kernel can be expanded or collapsed. Memories that do not belong to any kernel are shown under (Other).
2 RAM

A RAM is a memory that has at least one write to it. The name of the RAM memory is same as its name in your design.

When you select a memory name, you can view a logical representation of the RAM in the Kernel Memory Viewer pane. By default, only the first bank of the memory system is displayed.

To select banks that you want the Kernel Memory Viewer pane to display:

  1. Expand the memory name.
  2. Clear the memory name check box to collapse all memory banks in the view.
  3. Select the memory name check box to show all memory banks in the view.
3 ROM

A ROM is a memory that is read-only. The name of the ROM memory is same as its name in your design.

When you select a memory name, you can view a logical representation of the ROM in the Kernel Memory Viewer pane. By default, only the first bank of the memory system is displayed.

To select banks that you want the Kernel Memory Viewer pane to display:

  1. Expand the memory name.
  2. Clear the memory name check box to collapse all memory banks in the view.
  3. Select the memory name check box to show all memory banks in the view.
4 Bank #num Bank

A memory bank is always associated with a RAM or a ROM. Each bank is named as Bank #num, where #num is the ID of the memory bank starting from 0.

  • Click the bank name to display the bank view in the Kernel Memory Viewer pane, which displays a graphical representation of the bank with all of its replicates and private copies. This view can help you focus on specific memory banks of a complex memory design.
  • Clear the memory bank name check box to collapse the bank in the logical representation of the memory.
  • Select the memory bank name check box to display the bank in the logical representation of the memory.
5 Register

A register is a kernel variable that is carried through the pipeline in registers (rather than being stored in a RAM or ROM). The name of the register is same as its name in your design.

You can implement a register variable either exclusively in FFs or in a combination of FFs and RAM-based FIFOs.

6 text label Optimized Away

A kernel variable can be optimized away because it is unused in your design, or compiler optimizations have transformed all uses of the variable such that it is unnecessary. The name of the optimized away variable is same as its name in your design.

7 Filter

Use the Kernel Memory List filter to selectively view the list of RAMs, ROMs, registers, and optimized away variables in your design.

When you clear the check box associated with an item in the filter, you hide all occurrences of that kind of item in the Kernel Memory List. Filter your Kernel Memory List to help you focus on a specific type of memory in your design.

Kernel Memory Viewer

In the Kernel Memory Viewer pane, you can view connections between loads and stores to specific logical ports on the banks in a memory system. You can also view the number of replicates and private copies created per bank for your memory system. You can see the following types of nodes in the Kernel Memory Viewer pane, depending on the kernel memory system and what you have selected in the Kernel Memory List pane:

Table 2.  Node Types Observed in the Kernel Memory Viewer Pane
Node Type Description
Memory node The memory system for a given variable in your design.
Bank node A bank in the memory system. A memory system contains at least one bank. A memory bank can connect to one or more port nodes. Only banks selected in the Kernel Memory List pane are shown.
Replication node A replication node shows memory bank replicates that are created to efficiently support multiple accesses to a local memory. A bank contains at least one replicate. You can view replicate nodes only when you view a memory bank by clicking its name in the Kernel Memory List pane.
Private-copy node A private-copy node shows private copies within a replicate that are created to allow simultaneous execution of multiple loop iterations. A replicate contains at least one private copy. You can view private-copy nodes only when you view a memory bank by clicking its name in the Kernel Memory List pane.
Port node

Each read or write access to a local memory is mapped to a port. The logical port for a bank. There are three types of port:

  • R: A read-only port
  • W: A write-only port
  • RW: A read and write port
LSU node A store (ST) or load (LD) node connected to the memory through port nodes.
Arbitration node An arbitration (ARB) node shows that LSUs compete for access to a shared port node, which can lead to stalls.
Port-sharing node A port-sharing node (SHARE) shows that LSUs have mutually exclusive access to a shared port node, so the load-store units are free from stalls.

Within the graphical representation of a memory in the Kernel Memory View pane, you can do the following:

  • Hover over any node to view the attributes of that node.
  • Hover over an LSU node to highlight the path from the LSU node to all ports that the LSU connects to.
  • Hover over a port node to highlight the path from the port node to all LSUs that read or write to the port node.
  • Click a node to select it and display the node attributes in the Details pane.

The following images illustrate examples of what you see in the Kernel Memory Viewer:

Figure 21. Logical Representation of a Memory in Kernel Memory Viewer Pane
Figure 22. Bank View of a Memory Bank in Kernel Memory Viewer Pane

Code View

The code view pane displays your source code. When you select a memory or a bank in the Kernel Memory Viewer pane, the code view pane highlights the line of your code where you declared the memory.

Details

The Details pane shows the attributes of the node selected in the Kernel Memory Viewer pane. For example, when you select a memory in a kernel, the Details pane displays information such as:
  • width and depths of the memory banks
  • memory layout
  • address-bit mapping
  • memory attributes that you specified in your source code

The content of the Details pane persists until you select a different node in the Kernel Memory Viewer pane.