Intel® FPGA SDK for OpenCL™ Pro Edition: Best Practices Guide

ID 683521
Date 10/04/2021
Public

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10.6. Creating RTL Modules

You may embed RTL modules in an OpenCL kernel. For more information about how to integrate an RTL module into your OpenCL design, refer to the Understanding RTL Modules and the OpenCL Pipeline section.
To create an Intel® Stratix® 10 OpenCL-compatible RTL module, you must understand the Intel® Stratix® 10-specific changes to the reset signal, and know how to write compatibly pipelined interfaces to the RTL module.

For more information about Intel® Stratix® 10-specific RTL design best practices, refer to the Intel® Stratix® 10 High-Performance Design Handbook.

There are stall-free and stallable RTL modules. A stall-free RTL module is a fixed-latency module for which the offline compiler can optimize away stall logic. Refer to the Stall-Free RTL section in the Intel® FPGA SDK for OpenCL™ Pro Edition Programming Guide for more information.

A stallable RTL module has variable latency and relies on backpressured input and output interfaces to function correctly. Implementing stallable interfaces in Intel® Stratix® 10 designs consumes a lot of FPGA resources because of the handshake logic, which limits retiming. Using stallable interfaces in Intel® Stratix® 10 designs also disables the data path control optimization scheme.

Intel® strongly recommends that you use stall-free RTL modules because the offline compiler can incorporate them into your Intel® Stratix® 10 designs more effectively.

Note: There are important differences between the reset requirements for stall-free and stallable RTL modules. These requirements are necessary for the functional correctness of the RTL modules. For more information, refer to Intel® Stratix® 10 Design-Specific Reset Requirements for Stall-Free and Stallable RTL Modules in the Intel® FPGA SDK for OpenCL™ Pro Edition Programming Guide.