Multi Channel DMA Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683517
Date 7/30/2024
Public
Document Table of Contents

3.2.1. Procedure

  1. In the Quartus® Prime Pro Edition software, create a new project FileNew Project Wizard.
  2. Specify the Directory, Name, and Top-Level Entity.
  3. For Project Type, accept the default value, Empty project. Click Next.
  4. For Add Files click Next.
  5. For Family, Device & Board Settings, select Stratix® 10 (GX/SX/MX/TX/DX) or Agilex™ 7 F-Series or Agilex™ 7 I-Series and the Target Device for your design.
    Note: The selected device is only used if you select None in Step 10c below.
  6. Click Finish.
  7. In the IP Catalog locate and add the H-Tile Multichannel DMA Intel FPGA IP ( Stratix® 10 GX/MX devices), P-Tile Multichannel DMA Intel FPGA IP ( Stratix® 10 DX and Agilex™ 7 devices), F-Tile Multichannel DMA Intel FPGA IP or R-Tile Multichannel DMA Intel FPGA IP ( Agilex™ 7 devices), which brings up the IP Parameter Editor.
  8. In the New IP Variant dialog box, specify a name for your IP. Click Create.
  9. On the IP Settings tabs, specify the parameters for your IP variation.
  10. On the Example Designs tab, make the following selections:
    1. For Example Design Files, turn on the Simulation and Synthesis options. If you do not need these simulation or synthesis files, leaving the corresponding option(s) turned off significantly reduces the example design generation time.
    2. For Generated HDL Format, only Verilog is available in the current release.
    3. For Target Development Kit, select the appropriate option.
      Note: If you select None, the generated design example targets the device specified. Otherwise, the design example uses the device on the selected development board. If you intend to test the design in hardware, make the appropriate pin assignments in the .qsf file.
      Note: Appropriate pin assignments in the .qsf file must to be added before compilation in P/F/R Tiles when Enable CVP (Intel VSEC) option is checked, and when Target Development Kit is selected as None. Otherwise, example design compilation in Quartus® Prime throws an error in the Fitter stage.
    4. For Currently Selected Example Design, select a design example from a pulldown menu. Available design examples depends on the User Mode and Interface type setting in MCDMA Settings under IP Settings tab.
    Available design examples for the MCDMA or BAM+MCDMA or BAM+BAS+MCDMA modes and Avalon-ST Interface type:
    • PIO using MQDMA Bypass Mode
    • Packet Generate/Check
    • Device-side Packet Loopback
    Available design examples for the MCDMA or BAM+MCDMA or BAM+BAS+MCDMA modes and Avalon-MM Interface type:
    • PIO using MQDMA Bypass Mode
    • AVMM DMA
    Available design example for only BAM User mode:
    • PIO using MQDMA Bypass Mode
    Available design examples for BAM+BAS User mode:
    • PIO using MQDMA Bypass Mode
    • Traffic Generator / Checker
    Available design examples for Data Mover Only User mode:
    • PIO using MQDMA Bypass Mode
    • External descriptor controller
  11. Select Generate Example Design to create a design example that you can simulate and download to hardware. If you target one of the Intel FPGA development kits, the device on that board supersedes the device previously selected in the Quartus® Prime Pro Edition project if the devices are different. When the prompt asks you to specify the directory for your example design, you can choose to accept the default directory ./intel_pcie_mcdma_0_example_design or choose another directory.
  12. Click Close on Generate Example Design Completed message.
  13. Close the IP Parameter Editor. Click FileExit. When prompted with Save changes?, you do not need to save the .ip. Click Don’t Save.