Multi Channel DMA IP for PCI Express* Design Example User Guide

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ID 683517
Date 8/04/2025
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Design Example Detailed Description 3. Design Example Quick Start Guide 4. Multi Channel DMA FPGA IP for PCI Express Design Example User Guide Archives 5. Revision History for the Multi Channel DMA FPGA IP for PCI Express Design Example User Guide
1. Introduction x
1.1. Terms and Acronyms 1.2. MCDMA IP Modes
2. Design Example Detailed Description x
2.1. Design Example Overview 2.2. PIO using MCDMA Bypass Mode 2.3. Avalon-ST Packet Generate/Check 2.4. Avalon-ST Device-side Packet Loopback 2.5. Avalon-MM DMA 2.6. BAM_BAS Traffic Generator and Checker 2.7. External Descriptor Controller
2.1. Design Example Overview x
2.1.1. H-Tile MCDMA IP - Design Examples for Endpoint 2.1.2. P-Tile MCDMA IP - Design Examples for Endpoint 2.1.3. F-Tile MCDMA IP - Design Examples for Endpoint 2.1.4. R-Tile MCDMA IP - Design Examples for Endpoint 2.1.5. Design Example BAR Mappings 2.1.6. Design Example Driver Support
2.2. PIO using MCDMA Bypass Mode x
2.2.1. Avalon-ST PIO using MCDMA Bypass Mode 2.2.2. Avalon-MM PIO using MCDMA Bypass Mode
2.2.1. Avalon-ST PIO using MCDMA Bypass Mode x
2.2.1.1. Single-Port Avalon-ST PIO using MCDMA Bypass Mode
2.2.2. Avalon-MM PIO using MCDMA Bypass Mode x
2.2.2.1. Simulation Results 2.2.2.2. Hardware Test Results
2.3. Avalon-ST Packet Generate/Check x
2.3.1. Single-Port Avalon-ST Packet Generate/Check
2.3.1. Single-Port Avalon-ST Packet Generate/Check x
2.3.1.1. Simulation Waveforms 2.3.1.2. Simulation Log 2.3.1.3. Hardware Test Result
2.4. Avalon-ST Device-side Packet Loopback x
2.4.1. Simulation Results 2.4.2. Hardware Test Results
2.5. Avalon-MM DMA x
2.5.1. Simulation Results 2.5.2. Hardware Test Results
2.6. BAM_BAS Traffic Generator and Checker x
2.6.1. BAM_BAS Traffic Generator and Checker Example Design Register Map
2.7. External Descriptor Controller x
2.7.1. Registers 2.7.2. Hardware Test Results
2.7.1. Registers x
2.7.1.1. GCSR Registers (Base address 64’h00000) 2.7.1.2. QCSR Registers(Base address 64’h10000)
3. Design Example Quick Start Guide x
3.1. Design Example Directory Structure 3.2. Generating the Example Design using Quartus® Prime 3.3. Simulating the Design Example 3.4. Compiling the Example Design in Quartus® Prime 3.5. Running the Design Example Application on a Hardware Setup
3.2. Generating the Example Design using Quartus® Prime x
3.2.1. Procedure
3.3. Simulating the Design Example x
3.3.1. Testbench Overview 3.3.2. Supported Simulators 3.3.3. Example Testbench Flow for DMA Test with Avalon-ST Packet Generate/Check Design Example 3.3.4. Run the Simulation Script 3.3.5. Steps to Run the Simulation 3.3.6. View the Results
3.3.5. Steps to Run the Simulation x
3.3.5.1. Steps to Run the Simulation : QuestaSim* / Questa* Intel® FPGA Edition 3.3.5.2. Steps to Run the Simulation : VCS* / VCS* MX 3.3.5.3. Steps to Run the Simulation : Xcelium*
3.5. Running the Design Example Application on a Hardware Setup x
3.5.1. Hardware Requirements 3.5.2. Software Requirements 3.5.3. Set Up the Hardware and Program the FPGA 3.5.4. Configuration Changes from BIOS 3.5.5. Installing the Required Kernel Version for Ubuntu v24.04 3.5.6. Set the Boot Parameters 3.5.7. MCDMA Custom Driver 3.5.8. MCDMA DPDK Poll Mode Driver 3.5.9. MCDMA Kernel Mode Network Device Driver
3.5.7. MCDMA Custom Driver x
3.5.7.1. Prerequisites 3.5.7.2. PIO Test 3.5.7.3. DMA Test 3.5.7.4. BAM Test 3.5.7.5. BAS Test
3.5.7.1. Prerequisites x
3.5.7.1.1. Install the Linux Kernel Driver 3.5.7.1.2. Enable Virtual Function 3.5.7.1.3. Build and Install the User Space Library 3.5.7.1.4. Build the Reference Application
3.5.7.2. PIO Test x
3.5.7.2.1. Custom PIO Read Write Test
3.5.7.3. DMA Test x
3.5.7.3.1. Avalon-MM DMA (AVMM DMA) 3.5.7.3.2. Avalon-ST Device-side Packet Loopback (Device-side Packet Loopback) 3.5.7.3.3. Avalon-ST Packet Generate/Check (Packet Generate/Check) 3.5.7.3.4. External Descriptor Controller
3.5.7.3.2. Avalon-ST Device-side Packet Loopback (Device-side Packet Loopback) x
3.5.7.3.2.1. DMA Test Beyond 256 Channels
3.5.7.3.3. Avalon-ST Packet Generate/Check (Packet Generate/Check) x
3.5.7.3.3.1. DMA Test Beyond 256 Channels
3.5.8. MCDMA DPDK Poll Mode Driver x
3.5.8.1. Prerequisites 3.5.8.2. PIO Test 3.5.8.3. DMA Test 3.5.8.4. BAM Test 3.5.8.5. BAS Test
3.5.8.1. Prerequisites x
3.5.8.1.1. Install the PMD Driver 3.5.8.1.2. Bind the Device 3.5.8.1.3. Enable Virtual Function
3.5.8.3. DMA Test x
3.5.8.3.1. Avalon-MM DMA (AVMM DMA) 3.5.8.3.2. Avalon-ST Packet Generate/Check (Packet Generate/Check) 3.5.8.3.3. Avalon-ST Device-side Packet Loopback (Device-side Packet Loopback)
3.5.8.3.2. Avalon-ST Packet Generate/Check (Packet Generate/Check) x
3.5.8.3.2.1. DMA Test Beyond 256 Channels
3.5.8.3.3. Avalon-ST Device-side Packet Loopback (Device-side Packet Loopback) x
3.5.8.3.3.1. DMA Test Beyond 256 Channels
3.5.9. MCDMA Kernel Mode Network Device Driver x
3.5.9.1. Prerequisites 3.5.9.2. PIO Test 3.5.9.3. Ping Test
3.5.9.1. Prerequisites x
3.5.9.1.1. Build and Install Netdev Driver 3.5.9.1.2. Enable Virtual Function
1. Introduction
2. Design Example Detailed Description
3. Design Example Quick Start Guide
4. Multi Channel DMA FPGA IP for PCI Express Design Example User Guide Archives
5. Revision History for the Multi Channel DMA FPGA IP for PCI Express Design Example User Guide

1.2. MCDMA IP Modes

The following table summarizes the MCDMA IP variants, IP mode and FPGA Development Kit board supported for design example hardware test.

Table 2.  MCDMA IP Modes and FPGA Development Kit for Design Examples
MCDMA IP IP Mode FPGA Development Kit Board for Design Example Hardware Test
PCI Express Application Data Width Application Clock Frequency
MCDMA H-Tile Gen3 x16 512 bits 250 MHz

Stratix® 10 GX H-Tile Production FPGA Development Kit

Stratix® 10 MX H-Tile Production FPGA Development Kit
Gen3 x8 256 bits 250 MHz
MCDMA P-Tile Gen4x16 512 bits

Stratix® 10 DX: 400/350/200/175 MHz

Agilex™ 7: 500/450/400/350/250/225/200/175 MHz

Stratix® 10 DX FPGA Development Kit (Production)

Agilex™ 7 FPGA F-Series Development Kit (Production 1 P-Tile and E-Tile)

Gen4 1x8

Gen4 2x8

 256 bits

Stratix® 10 DX: 400/350/200/175 MHz

Agilex™ 7: 500/450/400/350/250/225/200/175 MHz
Gen3 x16 512 bits 250 MHz

Gen3 1x8

Gen3 2x8

 256 bits 250 MHz
MCDMA R-Tile

Gen5 2x8, Gen4 x16

512 bits

500/475/450/425/400 MHz

Agilex™ 7 FPGA I-Series Development Kit (ES 2 x R-Tile and 1 x F-Tile)

Agilex™ 7 FPGA I-Series Development Kit (ES1 2 x R-Tile and 1 x F-Tile)

Gen4 2x8, Gen3 x16, Gen3 2x8

512 bits

300/275/250 MHz

Gen5 4x4, Gen4 2x8

256 bits

500/475/450/425/400 MHz

Gen3 2x8, Gen4 4x4, Gen3 4x4

256 bits

300/275/250 MHz
Gen4 4x4 128 bits 500/475/450/425/400 MHz
Gen3 4x4 128 bits 300/275/250 MHz
MCDMA F-Tile Gen4 1x16 512 bits 500/400/350/250/225/200/175 MHz

Agilex™ 7 FPGA F-Series Development Kit (ES1 2 x F-Tile)

Agilex™ 7 FPGA F-Series Development Kit (Production 2 x F-Tile)

Gen4 1x8

Gen4 2x8

 256 bits 500/400/350/250/225/200/175 MHz
Gen3 1x16 512 bits 250 MHz

Gen3 1x8

Gen3 2x8

 256 bits 250 MHz

Gen4 1x4 (Endpoint mode)

 128 bits 350/400/450/500 MHz

Gen3 1x4 (Endpoint mode)

 128 bits 250 MHz
Note: Agilex™ 7 FPGA I-Series Development Kit (ES 2 x R-Tile and 1 x F-Tile) R-Tile A0 die revision supports only Gen5 2x8 / 512 bit, Gen4 2x8 / 512bits and Gen3 2x8 / 512 bits.
Note: Agilex™ 7 FPGA I-Series Development Kit (ES1 2 x R-Tile and 1 x F-Tile) R-Tile B0 die revision supports all PCIe Hard IP Modes defined in MCDMA R-Tile row

For more information about MCDMA IP, refer to the Multi Channel DMA IP for PCI Express User Guide.

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