Mailbox Client with Avalon® Streaming Interface Intel® FPGA IP User Guide

ID 683510
Date 10/04/2021

A newer version of this document is available. Customers should click here to go to the newest version. Clock and Reset Interfaces

Table 2.  Clock and Reset Interfaces
Signal Name Direction Description
in_clk Input This is the clock for the Avalon® streaming interfaces. The maximum frequency in 250 MHz.
in_reset Input This is an active high reset. Assert in_reset to reset the Mailbox Client with Avalon® streaming interface Intel® FPGA IP (Mailbox Client with Avalon® ST IP). When the in_reset signal asserts, the SDM must flush any pending activity from the Mailbox Client with Avalon® ST IP. The SDM continues to process commands from other clients.
To ensure the Mailbox Client with Avalon® ST IP functions correctly when the device enters user mode, your design must include the Reset Release Intel® FPGA IP to hold the reset until the FPGA fabric entered user mode. Intel recommends using a reset synchronizer when connecting the user reset or output of the Reset Release IP to the reset port of the Mailbox Client with Avalon® ST IP. To implement the reset synchronizer, use the Reset Bridge Intel® FPGA IP available in the Platform Designer.
Note: For IP instantiation and connection guidelines in the Platform Designer, refer to the Required Communication and Host Components for the Remote System Update Design Example figure in the Intel® Agilex™ Configuration User Guide.

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