R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 4/07/2025
Public

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Document Table of Contents

F.4.1. Avery BFM Configuration

In this example, the Avery BFM in the apci_top_rtile_tb.sv file is configured to support Gen5 1x16 PIPE mode simulations as the R-Tile PIO design example generated was in this mode. This is configured as shown below:

    `define APCI_NUM_LANES 16     //
        default: 16 lanes

rc.cfg_info.speed_sup = 5; // RC supporting Gen5 speed

If you have a Gen5 1x8 design, you can modify the testbench parameters as follows:

    `define APCI_NUM_LANES 8    //
        changed APCI_NUM_LANES to 8

The testbench can also be configured for serial vs PIPE mode simulation by adding a compile option as part of the simulation scripts set-up described in the next section.