Stratix® 10 10GBASE-KR PHY IP Core User Guide

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ID 683500
Date 5/03/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Stratix® 10 10GBASE-KR PHY IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Stratix® 10 10GBASE-KR PHY Registers 6. Interface Signals 7. Design Example 8. Supported Tools A. Difference between Stratix® 10 and Arria® 10 IP Variants B. Stratix® 10 10GBASE-KR PHY IP Core User Guide Archives C. Document Revision History for Stratix® 10 10GBASE-KR PHY IP Core User Guide
1. About the Stratix® 10 10GBASE-KR PHY IP Core x
1.1. Stratix® 10 10GBASE-KR PHY IP Core Supported Features 1.2. Device Family Support 1.3. IP Core Speed Grade Support 1.4. Resource Utilization 1.5. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. Simulating the IP Core 2.5. Integrating Your IP Core in Your Design 2.6. Stratix® 10 10GBASE-KR IP Core Testbench 2.7. Compiling the Full design
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your IP Core in Your Design x
2.5.1. Pin Assignments 2.5.2. Adding the Transceiver PLL 2.5.3. Adding the fPLL 2.5.4. Adding the Stratix® 10 Transceiver PHY Reset Controller 2.5.5. Placement Settings for the Stratix® 10 10GBASE-KR PHY IP Core
5. Stratix® 10 10GBASE-KR PHY Registers x
5.1. Register Map 5.2. Register Definitions
6. Interface Signals x
6.1. Clock and Reset Signals 6.2. Data Interface Signals 6.3. Serial Data Signals 6.4. Avalon® -MM Interface Signals 6.5. Transceiver Reconfiguration Signals 6.6. Control and Status Signals
6.2. Data Interface Signals x
6.2.1. XGMII Mapping to Standard SDR XGMII Data
7. Design Example x
7.1. Quick Start Guide 7.2. Design Example Description
7.1. Quick Start Guide x
7.1.1. Design Example Directory Structure 7.1.2. Hardware Design Example Components 7.1.3. Simulation Design Example Components 7.1.4. Generating the Design Example 7.1.5. Simulating the Stratix® 10 10GBASE-KR Design Example Testbench 7.1.6. Compiling and Configuring the Design Example in Hardware 7.1.7. Testing the Hardware Design Example
7.2. Design Example Description x
7.2.1. Hardware and Software Requirements 7.2.2. Design Example Behavior 7.2.3. Design Example Interface Signals 7.2.4. Stratix® 10 10GBASE-KR PHY Design Example Registers
8. Supported Tools x
8.1. Ethernet Toolkit Overview
8.1. Ethernet Toolkit Overview x
8.1.1. Features
1. About the Stratix® 10 10GBASE-KR PHY IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Stratix® 10 10GBASE-KR PHY Registers
6. Interface Signals
7. Design Example
8. Supported Tools
A. Difference between Stratix® 10 and Arria® 10 IP Variants
B. Stratix® 10 10GBASE-KR PHY IP Core User Guide Archives
C. Document Revision History for Stratix® 10 10GBASE-KR PHY IP Core User Guide

7.2.4. Stratix® 10 10GBASE-KR PHY Design Example Registers

Table 23.   Stratix® 10 10GBASE-KR Hardware Design Example Register MapLists the memory mapped register ranges for the hardware design example. You access these registers with the reconfig_read and reconfig_write functions in the System Console.

Word Offset

Name

Description

0x0000–0x07FF

 CH0_PHY Channel 0 Native PHY access

0x0800–0x08FF

 CH0_PHY Channel 0 10G-Base-KR IP CSR access
0x1000–0x17ff CH1_PHY Channel 1 Native PHY access
0x1800–0x18FF CH1_PHY Channel 1 10G-Base-KR IP CSR access
0xF000–0xFFFF Test Harness Refer to the table Test Harness Register Map
Note: For an example, to access 0x4B0 address of CH0 IP register, use the absolute address 0x4B0+0x800 that is 0xCB0.
Table 24.   Test Harness Register Map

Word Offset

Bit R/W Name

Description

0x00

 0 RWSC Start XGMII packets When set to 1, sends the specified number of XGMII packets.

0x01

 0 RW Reset Hold When set to 1, holds the channel in reset. This bit must be written to 0 for normal operation.
8 RW Generator Reset When set to 1, holds the XGMII and GMII generators in reset. Bit must be written to 0 for normal operation.

0x02

 0 R rx_data_ready When asserted, indicates the block synchronizer has successfully established synchronization. The incoming XGMII data block locks the receiver.
1 R XGMII checker_pass When asserted indicates that the received frames are exactly same as the transmitted frames. When XGMII rx_mismatch asserted, this is set to 0.
2 R XGMII rx_mismatch Asserted even if single received frame doesn't match the transmitted frame.
3 R XGMII fifo_full Shows the XGMII FIFO on the TX side is full. When set to 1, indicates error condition.
4 R test_done When asserted indicates that the transmitter sent all 418 frames. Each frame is 64-bit wide data and 2-bit control.
5 R XGMII frame_done When asserted indicates that the transmitter finished sending particular type of frames and then goes low automatically.
6 R XGMII test_pass When asserted, XGMII has received all sent packets and there is no mismatch in received data.

XGMII status= rx_data_ready & checker_pass & ! rx_mismatch

0x03

 Reserved
0x04 [31:0] RSC XGMII RX frame_count channel 0 Non-idle frame count on the RX side of channel 0. This is self clearing on read.
0x05–0xFF Reserved
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