Intel® Arria® 10 and Intel® Cyclone® 10 Avalon® Memory-mapped Interface for PCIe* Design Example User Guide

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ID 683476
Date 1/13/2022
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description A. Document Revision History for Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Memory-mapped Hard IP for PCIe Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Design Components for the Avalon® -MM Endpoint 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design in Hardware
2. Design Example Description x
2.1. Creating a Signal Tap Debug File to Match Your Design Hierarchy 2.2. Intel® Arria® 10 Development Kit Conduit Interface
1. Quick Start Guide
2. Design Example Description
A. Document Revision History for Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Memory-mapped Hard IP for PCIe Design Example User Guide

1.4. Simulating the Design

Figure 4. Procedure
  1. Change to the testbench simulation directory.
  2. Run the simulation script for the simulator of your choice. Refer to the table below.
  3. Analyze the results.
Table 1.  Steps to Run Simulation
Simulator Working Directory Instructions
ModelSim* <example_design>/pcie_example_design_tb/pcie_example_design_tb/sim/mentor/
  1. Invoke vsim
  2. do msim_setup.tcl
  3. ld_debug
  4. run -all
  5. A successful simulation ends with the following message, "Simulation stopped due to successful completion!"
VCS* <example_design>/pcie_example_design_tb/pcie_example_design_tb/sim/synopsys/vcs
  1. sh vcs_setup.sh USER_DEFINED_SIM_OPTIONS=""
  2. A successful simulation ends with the following message, "Simulation stopped due to successful completion!"
NCSim* <example_design>/pcie_example_design_tb/pcie_example_design_tb/sim/cadence
  1. sh ncsim_setup.sh USER_DEFINED_SIM_OPTIONS=""
  2. A successful simulation ends with the following message, "Simulation stopped due to successful completion!"
Xcelium* Parallel Simulator <example_design>/pcie_example_design_tb/pcie_example_design_tb/sim/xcelium
  1. sh xcelium_setup.sh USER_DEFINED_SIM_OPTIONS="" USER_DEFINED_ELAB_OPTIONS="-NOWARN\ CSINFI"
  2. A successful simulation ends with the following message, "Simulation stopped due to successful completion!"
Figure 5. Partial Transcript from Successful Endpoint Avalon-ST PIO Simulation Testbench
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