1.3. Generating the Design
- Launch Platform Designer.
- If you have an existing .qsys file in your directory, the Open System dialog box appears. Click New to specify a Quartus Prime project name and custom IP variation name for your design. Then, click Create.
- If not, a new project is automatically created. Save it before moving to the next step.
- In the IP Catalog, locate and select Intel® Arria® 10/Cyclone 10 Hard IP for PCI Express. The parameter editor appears.
- On the IP Settings tabs, specify the parameters for your IP variation.
- In the Connections panel, make the following dummy connection: rxm_bar0 to txs slave interface.
Platform Designer determines the size of the Avalon® -MM BAR master from its connection to an Avalon® -MM slave device. When you generate the example design, this connection is removed.
- Remove the clock_in and reset_in components that were instantiated by default.
- On the Example Design tab, the PIO design is available for your IP variation.
- For Example Design Files, select the Simulation and Synthesis options.
- For Generated HDL Format, only Verilog is available.
- For Target Development Kit, select the Intel® Arria® 10 GX FPGA Development Kit option. Currently, there is no option to select an Intel® Cyclone® 10 GX Development Kit when generating an example design.
- Click Generate Example Design. The software generates all files necessary to run simulations and hardware tests on the Intel® Arria® 10 FPGA Development Kit.
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