2.2. E-Tile Hard IP for Ethernet Intel FPGA IP Overview

E-Tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

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ID 683468

Date 2/02/2024

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2.2. E-Tile Hard IP for Ethernet Intel FPGA IP Overview

The E-Tile Hard IP for Ethernet Intel FPGA IP block diagrams show the main blocks, and internal and external connections for each variant.

For these block diagrams, the reconfiguration and soft reset sequencer implement the reconfiguration interfaces and resets for the core, respectively. The auto-negotiation and link training (AN/LT) soft logic is only inserted when you select Enable AN/LT.

Figure 2. Single 10G/25G Channel

This variant supports only single channel 10G/25G Ethernet without RS-FEC and PTP features.

Figure 3. 1 to 4 10G/25G Channels with Optional RS-FEC

This variant of the IP core includes up to four channels. Each channel has its own set of adapters, reconfiguration logic, AN/LT and reset sequencer logic.
RS-FEC is optional for this variant.

Figure 4. 100G Channel with Optional RS-FEC

This variant of the IP core includes a single 100G channel that has its own set of adapters, reconfiguration logic, AN/LT and reset sequencer logic.
The deskew logic corrects for possible skew over the EMIB interfaces between the main die and the E-tile.
RS-FEC is optional for this variant. You can select RS-FEC(528,514) or RS-FEC(544,514) for this variant.

Figure 5. 100G Channel with 1 to 4 10G/25G Channels, RS-FEC, and Precision Time Protocol (PTP)

This variant of the IP core includes a 100G channel or between 1 to 4 10G/25G channels.
Because the 100G channel uses the same transceivers as the 10G/25G channels, you cannot use the 100G channel when any of the 10G/25G channels are running. You can switch the reconfiguration interfaces on the core between channels at run time.
For this variant, each channel has its own set of adapters, reconfiguration logic, AN/LT and reset sequencer logic.
The deskew logic corrects for possible skew over the EMIB interfaces between the main die and the E-tile. The EMIB deskew logic is always used for 100G channels. For 10G/25G channels, the deskew logic is used when you enable PTP, to ensure the PTP commands to each channel are synchronized to data. The deskew logic is not required for single 10G/25G channel.
The PTP soft component logic block provides the user PTP interface, performs the soft logic operations required for the E-tile timestamp system, and interacts with the TOD module (the Time-of-Day clock) that you provide.
RS-FEC and PTP are optional for this variant. This variant only supports RS-FEC(528,514) with PTP enabled.

Figure 6. Custom PCS with Optional RS-FEC

This variant of IP core supports customizable line rate PCS up to four channels. Each channel has its own set of adapters, reconfiguration logic, and reset sequencer logic. This variant does not include an Ethernet MAC.
This variant supports transceiver line rates ranges from 2.5 to 28 Gbps used in other protocols.
RS-FEC is optional for this variant and it supports RS-FEC for Ethernet and Fibre Channel modes.

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E-Tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

2.2. E-Tile Hard IP for Ethernet Intel FPGA IP Overview