Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 1.2 Errata

Download PDF
ID 683462
Date 12/04/2018
Public
Document Table of Contents
Document Table of Contents x
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 1.2 Errata
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 1.2 Errata x
Flash Fallback Does Not Meet PCIe Timeout Unsupported Transaction Layer Packet Types fpgainfo errors -c Does Not Clear the Error Response When Non-Fatal Errors Occur Board management controller does not verify the CRC in a PLDM request. The 1.2 V current and 1.8 V voltage upper non-recoverable (UNR) limits for the board management controller and the pacd are set to the same value. Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs v1.2 Errata Revision History
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 1.2 Errata

Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs v1.2 Errata Revision History

Date Intel® Acceleration Stack Version Changes
2018.12.04 1.2 (compatible with Intel® Quartus® Prime Pro Edition 17.1.1) Initial release.
Level Two Title