Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 1.2 Errata

ID 683462
Date 12/04/2018
Public

Unsupported Transaction Layer Packet Types

Description

The Acceleration Stack FPGA Interface Manager (FIM) does not support PCIe* Memory Read Lock, Configuration Read Type 1, and Configuration Write Type 1 transaction layer packets (TLPs). If the device receives a PCIe* packet of this type, it does not respond with a Completion packet as expected.

Workaround

No workaround available.

Status

No planned fix

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