Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 1.2 Errata

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ID 683462
Date 12/04/2018
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Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 1.2 Errata
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 1.2 Errata x
Flash Fallback Does Not Meet PCIe Timeout Unsupported Transaction Layer Packet Types fpgainfo errors -c Does Not Clear the Error Response When Non-Fatal Errors Occur Board management controller does not verify the CRC in a PLDM request. The 1.2 V current and 1.8 V voltage upper non-recoverable (UNR) limits for the board management controller and the pacd are set to the same value. Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs v1.2 Errata Revision History
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 1.2 Errata

Unsupported Transaction Layer Packet Types

Description

The Acceleration Stack FPGA Interface Manager (FIM) does not support PCIe* Memory Read Lock, Configuration Read Type 1, and Configuration Write Type 1 transaction layer packets (TLPs). If the device receives a PCIe* packet of this type, it does not respond with a Completion packet as expected.

Workaround

No workaround available.

Status

No planned fix

Level Two Title