Intel® High Level Synthesis Compiler Pro Edition: User Guide

ID 683456
Date 6/26/2023

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Document Table of Contents

A.2.3. Schedule Viewer (Beta)

Use the Schedule Viewer to identify latency bottlenecks in your design. The Schedule Viewer shows the estimated start and ending clock cycle for functions, blocks, clusters, and individual instructions in your design.

The viewer also shows the dependencies between block and instructions in your designs with connecting lines. These dependency lines indicate the order of execution for the blocks and instructions.

Click an item in the Schedule List to focus the Schedule View at the selected level. You cannot click the system level of the component hierarchy in the Schedule List.

Click the schedule bar for an item in the Schedule View updates the Details pane with the information available about that item. The information can include a description of the item, start cycle, and latency.

Click an item in the Schedule View to show a popup menu for the item. For instructions, the popup menu includes a link that takes you to your C++ code that resulted in that instruction.

Hover over a node in the diagram to highlight its outgoing dependency lines.