JESD204B Intel® FPGA IP User Guide

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ID 683442
Date 7/20/2023
Public
Document Table of Contents
Document Table of Contents x
1. JESD204B IP Quick Reference 2. About the JESD204B Intel® FPGA IP 3. Getting Started 4. JESD204B IP Functional Description 5. JESD204B IP Deterministic Latency Implementation Guidelines 6. JESD204B IP Debug Guidelines 7. JESD204B Intel® FPGA IP User Guide Archives 8. Document Revision History for the JESD204B Intel® FPGA IP User Guide
2. About the JESD204B Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. Datapath Modes 2.4. IP Variation 2.5. JESD204B IP Configuration 2.6. Channel Bonding 2.7. Performance and Resource Utilization
2.5. JESD204B IP Configuration x
2.5.1. Run-Time Configuration
3. Getting Started x
3.1. Introduction to Intel® FPGA IP Cores 3.2. Installing and Licensing Intel® FPGA IP Cores 3.3. Intel® FPGA IP Evaluation Mode 3.4. Upgrading IP Cores 3.5. IP Catalog and Parameter Editor 3.6. Design Walkthrough 3.7. JESD204B Design Examples 3.8. JESD204B IP Design Considerations 3.9. JESD204B Intel® FPGA IP Parameters 3.10. JESD204B IP Component Files 3.11. JESD204B IP Testbench
3.6. Design Walkthrough x
3.6.1. Creating a New Intel® Quartus® Prime Project 3.6.2. Parameterizing and Generating the IP 3.6.3. Compiling the JESD204B IP Core Design 3.6.4. Programming an FPGA Device
3.8. JESD204B IP Design Considerations x
3.8.1. Integrating the JESD204B IP in Platform Designer 3.8.2. Pin Assignments 3.8.3. Adding External Transceiver PLLs 3.8.4. Timing Constraints For Input Clocks
3.11. JESD204B IP Testbench x
3.11.1. Generating and Simulating the IP Testbench 3.11.2. Testbench Simulation Flow
3.11.1. Generating and Simulating the IP Testbench x
3.11.1.1. Generating the Testbench Simulation Model 3.11.1.2. Simulating the IP Testbench
4. JESD204B IP Functional Description x
4.1. Transmitter 4.2. Receiver 4.3. Operation 4.4. Clocking Scheme 4.5. Reset Scheme 4.6. Signals 4.7. Registers
4.1. Transmitter x
4.1.1. TX Data Link Layer 4.1.2. TX PHY Layer
4.1.1. TX Data Link Layer x
4.1.1.1. TX CGS 4.1.1.2. TX ILAS 4.1.1.3. User Data Phase
4.2. Receiver x
4.2.1. RX Data Link Layer 4.2.2. RX PHY Layer
4.2.1. RX Data Link Layer x
4.2.1.1. RX CGS 4.2.1.2. Frame Synchronization 4.2.1.3. Frame Alignment 4.2.1.4. Lane Alignment 4.2.1.5. ILAS Data 4.2.1.6. Initial Lane Synchronization
4.3. Operation x
4.3.1. Operating Modes 4.3.2. Scrambler/Descrambler 4.3.3. SYNC_N Signal 4.3.4. Link Reinitialization 4.3.5. Link Startup Sequence 4.3.6. Error Reporting Through SYNC_N Signal
4.3.1. Operating Modes x
4.3.1.1. Subclass 0 Operating Mode 4.3.1.2. Subclass 1 Operating Mode 4.3.1.3. Subclass 2 Operating Mode
4.4. Clocking Scheme x
4.4.1. Device Clock 4.4.2. Link Clock 4.4.3. Local MultiFrame Clock 4.4.4. Clock Correlation 4.4.5. Transceiver Calibration Clock Source
4.5. Reset Scheme x
4.5.1. Reset Sequence 4.5.2. ADC–FPGA Subsystem Reset Sequence 4.5.3. FPGA–DAC Subsystem Reset Sequence
4.6. Signals x
4.6.1. Transmitter Signals 4.6.2. Receiver Signals
4.7. Registers x
4.7.1. Register Access Type Convention 4.7.2. Transmitter Registers 4.7.3. Receiver Registers
5. JESD204B IP Deterministic Latency Implementation Guidelines x
5.1. SYSREF Guidelines 5.2. Constraining Incoming SYSREF Signal 5.3. Programmable RBD Offset 5.4. Programmable LMFC Offset 5.5. Maintaining Deterministic Latency during Link Reinitialization
6. JESD204B IP Debug Guidelines x
6.1. Clocking Scheme 6.2. JESD204B Parameters 6.3. SPI Programming 6.4. Converter and FPGA Operating Conditions 6.5. Signal Polarity and FPGA Pin Assignment 6.6. Creating a Signal Tap Debug File to Match Your Design Hierarchy 6.7. Debugging JESD204B Link Using System Console
6.6. Creating a Signal Tap Debug File to Match Your Design Hierarchy x
6.6.1. Removing Irrelevant Signals and Adding E-Tile PHY Signals
1. JESD204B IP Quick Reference
2. About the JESD204B Intel® FPGA IP
3. Getting Started
4. JESD204B IP Functional Description
5. JESD204B IP Deterministic Latency Implementation Guidelines
6. JESD204B IP Debug Guidelines
7. JESD204B Intel® FPGA IP User Guide Archives
8. Document Revision History for the JESD204B Intel® FPGA IP User Guide

3.9. JESD204B Intel® FPGA IP Parameters

Table 15.   JESD204B Intel® FPGA IP Parameters
Parameter Value Description
Main Tab
Device Family
  • Intel Agilex® 7
  • Intel® Stratix® 10
  • Intel® Arria® 10
  • Intel® Cyclone® 10 GX
  • Stratix® V
  • Cyclone® V
  • Arria® V
  • Arria® V GZ
The targeted device family.
JESD204B Wrapper
  • Base Only
  • PHY Only
  • Both Base and PHY
Select the JESD204B wrapper.
  • Base Only—generates the DLL only.
  • PHY Only—generates the transceiver PHY layer only (soft and hard PCS).
  • Both Base and PHY—generates both DLL and transceiver PHY layers.
Data Path
  • Receiver
  • Transmitter
  • Duplex

Select the operation modes. This selection enables or disables the receiver and transmitter supporting logic.

  • RX—instantiates the receiver to interface to the ADC.
  • TX—instantiates the transmitter to interface to the DAC.
  • Duplex—instantiates the receiver and transmitter to interface to both the ADC and DAC.

JESD204B Subclass

  • 0
  • 1
  • 2

Select the JESD204B subclass modes.

  • 0—Set subclass 0
  • 1—Set subclass 1
  • 2—Set subclass 2

Data Rate

1.0–19.2

Set the data rate for each lane.

  • Intel Agilex® 7 (E-tile)—2.0 Gbps to 19.2 Gbps
  • Intel® Stratix® 10 (L-tile, H-tile, and E-tile)—2.0 Gbps to 16.0 Gbps
  • Intel® Cyclone® 10 GX—2.0 Gbps to 6.25 Gbps
  • Intel® Arria® 10—2.0 Gbps to 15.0 Gbps
  • Stratix® V—2.0 Gbps to 12.5 Gbps
  • Cyclone® V—1.0 Gbps to 5.0 Gbps
  • Arria® V—1.0 Gbps to 7.5 Gbps
  • Arria® V GZ—2.0 Gbps to 9.9 Gbps
Note: The maximum data rate is limited due to different device speed grades, transceiver PMA speed grades, and PCS options. Refer to Performance and Resource Utilization for the maximum data rate support.

Transceiver Tile
  • E-tile
  • H-tile

This option is available only when you target an Intel® Stratix® 10 device that supports both H-tile and E-tile. Select the transceiver tile you want for your design.

When you select E-tile, you can only use soft PCS.

Note: For simplex variants with E-tile transceiver, the underneath transceiver is in duplex mode. The merging of independent TX and RX within a transceiver channel is not supported in this version.

PCS Option

  • Enabled Hard PCS
  • Enabled Soft PCS
  • Enabled PMA Direct

Select the PCS modes.

  • Enabled Hard PCS—use Hard PCS components. Select this option to minimize resource utilization with data rate that supports up to the limitation of the Hard PCS.
    Note: For this setting, use 8G PCS mode with 20 bits PMA width and 32-bit PCS width.
  • Enabled Soft PCS—use Soft PCS components. Select this option to allow higher supported data rate but increases the resource utilization. This option is applicable for all devices except Cyclone® V and Arria® V GT/ST.
    Note: For this setting, use 10G PCS mode with 40 bits PMA width and 40 bits PCS width.
  • Enabled PMA Direct—Native PHY is set to PMA Direct mode. Select this option to allow the highest supported data rate and to maximize the resource utilization. This option is applicable only for Arria® V GT/ST devices.
    Note: For this setting, use PMA Direct mode with 80-bit PMA width.

PLL Type

  • CMU
  • ATX

Select the phase-locked loop (PLL) types, depending on the FPGA device family. This parameter is not applicable to Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.

  • Cyclone® V—CMU
  • Arria® V—CMU
  • Stratix® V—CMU, ATX
Bonding Mode
  • Bonded
  • Non-bonded

Select the bonding modes.

  • Bonded—select this option to minimize inter-lanes skew for the transmitter datapath.
  • Non-bonded—select this option to disable inter-lanes skew control for the transmitter datapath.
Note: For Stratix® V, Arria® V, and Cyclone® V devices, the bonding type is automatically selected based on the device family and number of lanes that you set.

PLL/CDR Reference Clock Frequency

Variable

Set the transceiver reference clock frequency for PLL or CDR.

  • For Stratix® V, Arria® V, and Cyclone® V devices, the frequency range available for you to choose depends on the PLL type and data rate that you select.
  • For Intel Agilex® 7, Intel® Stratix® 10, Intel® Cyclone® 10 GX, and Intel® Arria® 10 devices, the frequency range available for you to choose depends on the data rate.

VCCR_GXB and VCCT_GXB Supply Voltage for the Transceiver

  • 1.1V
  • 1.0V
 Select the supply voltage for the transceiver.

For details about the minimum, typical, and maximum supply voltage specifications, refer to the Intel® Stratix® 10 Device Datasheet.

Note: Available only for Intel® Stratix® 10 L-tile and H-tile devices.

Enable Bit reversal and Byte reversal

On, Off

The JESD204B IP uses four 10-bit symbols (denoted as symbol3, symbol2, symbol1, and symbol0) for the 8B/10B encoding scheme. Symbol0 is the first symbol to be shifted out through the serial link while symbol3 is the last symbol to be shifted out.

  • Turn off this option to set the data transmission order to start from the least significant bit (lsb) of each symbol. For example, symbol0[0] is shifted out first, followed by symbol0[1], and so on until the entire symbol0 is shifted out. The transmission continues with symbol1[0] through symbol3[9].
  • Turn on this option to set the data transmission order to start from the most significant bit (lsb) of each symbol. For example, symbol0[9] is shifted out first, followed by symbol0[8], and so on until the entire symbol0 is shifted out. The transmission continues with symbol1[9] through symbol3[0].
Enable Transceiver Dynamic Reconfiguration

On, Off

Turn on this option to enable dynamic data rate change. For V series devices, when you enable this option, you need to connect the reconfiguration interface to the transceiver reconfiguration controller. 18

For Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices, turn on this option to enable the Transceiver Native PHY reconfiguration interface.

Enable Native PHY Debug Master Endpoint 19 On, Off Turn on this option for the Transceiver Native PHY IP core to include an embedded Native PHY Debug Master Endpoint. This block connects internally to the Avalon® memory-mapped slave interface of the Transceiver Native PHY and can access the reconfiguration space of the transceiver. It can perform certain test and debug functions via JTAG using System Console.

This parameter is valid only when you turn on the Enable Transceiver Dynamic Reconfiguration parameter.

Note: Available only for Intel Agilex® 7, Intel® Stratix® 10, Intel® Cyclone® 10 GX, and Intel® Arria® 10 devices.
Share Reconfiguration Interface 19 On, Off

When enabled, Transceiver Native PHY presents a single Avalon® memory-mapped slave interface for dynamic reconfiguration of all channels. In this configuration the upper address bits ( Intel® Stratix® 10: [log2<L>+10:11]; Intel® Arria® 10/ Intel® Cyclone® 10 GX: [log2<L>+9:10]) of the reconfiguration address bus specify the selected channel. The upper address bits only exist when L>1. Address bits ( Intel® Stratix® 10: [10:0]; Intel® Arria® 10/ Intel® Cyclone® 10 GX: [9:0]) provide the register offset address within the reconfiguration space of the selected channel. L is the number of channel.

When disabled, the Native PHY IP core provides an independent reconfiguration interface for each channel. For example, when a reconfiguration interface is not shared for a four-channel Native PHY IP instance, reconfig_address[9:0] corresponds to the reconfiguration address bus of logical channel 0, reconfig_address[19:10] correspond to the reconfiguration address bus of logical channel 1, reconfig_address[29:20] corresponds to the reconfiguration address bus of logical channel 2, and reconfig_address[39:30] correspond to the reconfiguration address bus of logical channel 3.

For configurations using more than one channel, this option must be enabled when you turn on Enable Native PHY Debug Master Endpoint.

Note: Available only for Intel Agilex® 7, Intel® Stratix® 10, Intel® Cyclone® 10 GX, and Intel® Arria® 10 devices.
Provide Separate Reconfiguration Interface for Each Channel On, Off When enabled, transceiver dynamic reconfiguration interface presents separate clock, reset, and Avalon® memory-mapped slave interface for each channel instead of a single wide bus. This option is only available when Share Reconfiguration Interface is turned off.
Note: Available in Intel® Quartus® Prime Pro Edition only.
Enable Capability Registers 19 On, Off Turn on this option to enable capability registers, which provides high level information about the transceiver channel's configuration.
Note: Available only for Intel Agilex® 7, Intel® Stratix® 10, Intel® Cyclone® 10 GX, and Intel® Arria® 10 devices.
Set user-defined IP identifier 0–255 Set a user-defined numeric identifier that can be read from the user identifier offset when you turn on the Enable Capability Registers parameter.
Note: Available only for Intel Agilex® 7, Intel® Stratix® 10, Intel® Cyclone® 10 GX, and Intel® Arria® 10 devices.
Enable Control and Status Registers 19 On, Off Turn on this option to enable soft registers for reading status signals and writing control signals on the PHY interface through the embedded debug. For more information, refer to the respective Transceiver User Guides.
Note: Available only for Intel Agilex® 7, Intel® Stratix® 10, Intel® Cyclone® 10 GX, and Intel® Arria® 10 devices.
Enable PRBS Soft Accumulators 19 On, Off Turn on this option to set the soft logic to perform pseudorandom binary sequence (PRBS) bit and error accumulation when using the hard PRBS generator and checker.
Note: Available only for Intel Agilex® 7, Intel® Stratix® 10, Intel® Cyclone® 10 GX, and Intel® Arria® 10 devices.
JESD204B Configurations Tab

Lanes per converter device (L)

1–8

Set the number of lanes per converter device.

Note: Refer to Performance and Resource Utilization for the common supported range for L and the resource utilization.

Converters per device (M)

1–256

Set the number of converters per converter device.

Enable manual F configuration On, Off

Turn on this option to set parameter F in manual mode and enable this parameter to be configurable. Otherwise, the parameter F is in derived mode.

You have to enable this parameter and configure the appropriate F value if the transport layer in your design is supporting Control Word (CF) or High Density format(HD), or both.

Note: The auto derived F value using formula F= M*N'*S/(8*L) may not apply if parameter CF or parameter HD, or both are enabled.

Octets per frame (F)

  • 1–256 (for Intel® Stratix® 10 devices only)
  • 1, 2, 4–256 (for non Intel® Stratix® 10 devices)

The number of octets per frame is derived from F= M*N'*S/(8*L).

Converter resolution (N)

1–32

Set the number of conversion bits per converter.

Transmitted bits per sample (N')

1–32

Set the number of transmitted bits per sample (JESD204 word size, which is in nibble group).

Note: If parameter CF equals to 0 (no control word), parameter N' must be larger than or equal to sum of parameter N and parameter CS (N' ≥ N + CS). Otherwise, parameter N' must be larger than or equal to parameter N (N'≥N).

Samples per converter per frame (S)

1–32

Set the number of transmitted samples per converter per frame.

Frames per multiframe (K)

1–32

Set the number of frames per multiframe. This value is dependent on the value of F and is derived using the following constraints:
  • The value of K must fall within the range of 17/F <= K <= min(32, floor (1024/F))
  • The value of F*K must be divisible by 4

Enable scramble (SCR)

On, Off

Turn on this option to scramble the transmitted data or descramble the receiving data.

Control Bits (CS)

0–3

Set the number of control bits per conversion sample.

Control Words (CF)

0–32

Set the number of control words per frame clock period per link.

High density user data format (HD)

On, Off

Turn on this option to set the data format. This parameter controls whether a sample may be divided over more lanes.

  • On: High Density format
  • Off: Data should not cross the lane boundary

Enable Error Code Correction (ECC_EN)

On, Off

Turn on this option to enable error code correction (ECC) for memory blocks.

Phase adjustment request (PHADJ)

On, Off

Turn on this option to specify the phase adjustment request to the DAC.

  • On: Request for phase adjustment
  • Off: No phase adjustment

This parameter is valid for Subclass 2 mode only.

Adjustment resolution step count (ADJCNT)

0–15

Set the adjustment resolution for the DAC LMFC.

This parameter is valid for Subclass 2 mode only.

Direction of adjustment (ADJDIR)
  • Advance
  • Delay

Select to adjust the DAC LMFC direction.

This parameter is valid for Subclass 2 mode only.

Configurations and Status Registers Tab

Device ID

0–255

Set the device ID number.

Bank ID

0–15

Set the device bank ID number.

Lane# ID

0–31

Set the lane ID number.

Lane# checksum

0–255

Set the checksum for each lane ID.

Note: The PMA Adaptation parameters are available only for Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices. For more information about the PMA Adaptation parameters, refer to the PMA Adaptation section in the E-tile Transceiver PHY User Guide.
Related Information
18 To perform dynamic reconfiguration, you have to instantiate the Transceiver Reconfiguration Controller from the IP Catalog and connect it to the JESD204B IP core through the reconfig_to_xcvr and reconfig_from_xcvr interface.
19 To support the Transceiver Toolkit in your design, you must turn on this option.
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