1. JESD204B IP Quick Reference
2. About the JESD204B Intel® FPGA IP
3. Getting Started
4. JESD204B IP Functional Description
5. JESD204B IP Deterministic Latency Implementation Guidelines
6. JESD204B IP Debug Guidelines
7. JESD204B Intel® FPGA IP User Guide Archives
8. Document Revision History for the JESD204B Intel® FPGA IP User Guide
3.1. Introduction to Intel® FPGA IP Cores
3.2. Installing and Licensing Intel® FPGA IP Cores
3.3. Intel® FPGA IP Evaluation Mode
3.4. Upgrading IP Cores
3.5. IP Catalog and Parameter Editor
3.6. Design Walkthrough
3.7. JESD204B Design Examples
3.8. JESD204B IP Design Considerations
3.9. JESD204B Intel® FPGA IP Parameters
3.10. JESD204B IP Component Files
3.11. JESD204B IP Testbench
3.8.3. Adding External Transceiver PLLs
The JESD204B IP core variations that target an Stratix® 10 L-tile, Stratix® 10 H-tile, Arria® 10, or Cyclone® 10 GX FPGA device, require external transceiver PLLs for compilation. Select medium bandwidth for the PLL settings.
Note: For Agilex™ 7 and Stratix® 10 E-tile devices, the transceiver PLL is within the transceiver itself; so the design does not require external PLLs.
JESD204B IP variations that target an Arria V, Cyclone V, or Stratix V FPGA device contain transceiver PLLs. Therefore, no external PLLs are required for compilation.
Intel recommends that you follow the PLL recommendations in the respective Transceiver PHY user guides based on the data rates.
Note: The PMA width is 20 bits for Hard PCS and 40 bits for Soft PCS.