1. JESD204B IP Quick Reference
2. About the JESD204B Intel® FPGA IP
3. Getting Started
4. JESD204B IP Functional Description
5. JESD204B IP Deterministic Latency Implementation Guidelines
6. JESD204B IP Debug Guidelines
7. JESD204B Intel® FPGA IP User Guide Archives
8. Document Revision History for the JESD204B Intel® FPGA IP User Guide
3.1. Introduction to Intel® FPGA IP Cores
3.2. Installing and Licensing Intel® FPGA IP Cores
3.3. Intel® FPGA IP Evaluation Mode
3.4. Upgrading IP Cores
3.5. IP Catalog and Parameter Editor
3.6. Design Walkthrough
3.7. JESD204B Design Examples
3.8. JESD204B IP Design Considerations
3.9. JESD204B Intel® FPGA IP Parameters
3.10. JESD204B IP Component Files
3.11. JESD204B IP Testbench
5.5. Maintaining Deterministic Latency during Link Reinitialization
Link reinitialization occurs when the RX device deasserts the SYNC_N signal after link is established.
The converters resample the SYSREF signal and reset the internal LMFC counter. When the link is initially established, the IP core automatically clears the csr_sysref_singledet bit in the syncn_sysref_ctrl register (address 0x54) when it detects the SYSREF pulse. The IP core does not automatically resample the SYSREF pulse unless the jesd204_tx_avs_rst_n or jesd204_rx_avs_rst_n signal is asserted.
If you are performing a link reset by asserting txlink_rst_n or rxlink_rst_n to reinitialize the link, set the csr_sysref_singledet bit to "1" to force the IP core to resample the SYSREF pulse without asserting the jesd204_tx_avs_rst_n or jesd204_rx_avs_rst_n signal.