Generic Serial Flash Interface Intel® FPGA IP User Guide

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ID 683419
Date 4/24/2025
Public
Document Table of Contents
Document Table of Contents x
1. Generic Serial Flash Interface Intel® FPGA IP User Guide
1. Generic Serial Flash Interface Intel® FPGA IP User Guide x
1.1. Release Information 1.2. Device Family Support 1.3. Signals 1.4. Parameters 1.5. Register Map 1.6. Using Generic Serial Flash Interface Intel® FPGA IP 1.7. Generic Serial Flash Interface Intel® FPGA IP Reference Design 1.8. Flash Access Using the Generic Serial Flash Interface Intel® FPGA IP 1.9. Intel HAL Driver 1.10. Generic Serial Flash Interface Intel® FPGA IP User Guide Archives 1.11. Document Revision History for the Generic Serial Flash Interface Intel® FPGA IP User Guide
1.6. Using Generic Serial Flash Interface Intel® FPGA IP x
1.6.1. Control Status Register Byte Enable 1.6.2. Memory Operations 1.6.3. Byte Enabling 1.6.4. Constraining the I/O Pins
1.6.3. Byte Enabling x
1.6.3.1. Byte Enabling Supported Patterns
1.6.4. Constraining the I/O Pins x
1.6.4.1. General Purpose I/O 1.6.4.2. Dedicated Active Serial Interface
1.7. Generic Serial Flash Interface Intel® FPGA IP Reference Design x
1.7.1. Hardware and Software Requirements 1.7.2. Functional Description 1.7.3. Creating Nios® II Hardware System 1.7.4. Integrating Modules into Quartus® Prime Project 1.7.5. Programming the .sof File 1.7.6. Building Application Software System using Nios® II Software Build Tools
1.7.2. Functional Description x
1.7.2.1. Reference Design Components 1.7.2.2. Reference Design Application Program
1.7.6. Building Application Software System using Nios® II Software Build Tools x
1.7.6.1. Reference Design Results
1.8. Flash Access Using the Generic Serial Flash Interface Intel® FPGA IP x
1.8.1. Flash Operations that Require Operation Code 1.8.2. Flash Operations to Read Flash Registers 1.8.3. Flash Operations to Write Flash Registers 1.8.4. Flash Operations that Require An Address 1.8.5. Read Memory from the Flash 1.8.6. Program Flash
1.9. Intel HAL Driver x
1.9.1. Driver API
1. Generic Serial Flash Interface Intel® FPGA IP User Guide

1.9. Intel HAL Driver

The HAL API is available for this controller in the following software files:
  • intel_generic_serial_flash_interface_top.h
  • intel_generic_serial_flash_interface_top.c

These files implement the Generic Serial Flash Interface core device driver for the HAL system library.

Intel HAL supports a number of generic device model classes including one for device flashes. Developing against these generic classes gives a consistent interface for driver functions so that the HAL can access the driver functions uniformly.

A HAL API application begins by calling alt_flash_open_dev() to open the flash device, which returns a file handle to a flash device. You can obtain the IP name from system.h. All offset-related variables are based on absolute addressing to the flash memory.

HAL API supports the following QSPI flash device families:

  • Micron (MT25QL and MT25QU variants)
  • Cypress (S25FL-S and S25FS-S variants)
  • Macronix (MX25L and MX66U variants)
  • Winbond (W25Q variant)
  • GigaDevice (GD55LB variant)
  • ISSI (I25LP and I25WP variants)
Note: The Intel HAL Driver is supported in Quartus® Prime Pro Edition software only.
Note: Enable altera_safelib in BSP Software Package from BSP Editor to use the HAL API for Quartus® Prime Pro Edition software version prior to 21.4.
Note: Flash_Timeout is configurable in the Board Support Package Editor with the default value of 700000 microseconds (0.7 seconds).

Section Content
Driver API

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