NCO Intel® FPGA IP User Guide

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ID 683406
Date 10/20/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the NCO IP 2. NCO IP Getting Started 3. NCO IP Functional Description 4. NCO IP User Guide Document Archives 5. Document Revision History for the NCO IP User Guide
1. About the NCO IP x
1.1. DSP Intel® FPGA IP Features 1.2. NCO IP Features 1.3. NCO Intel® FPGA IP Device Family Support 1.4. NCO IP Verification 1.5. NCO IP Release Information
2. NCO IP Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition) 2.4. Simulating Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. NCO IP Core Intel® FPGA IP Evaluation Mode Timeout Behavior
2.3. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition) x
2.3.1. IP Core Generation Output ( Quartus® Prime Pro Edition)
3. NCO IP Functional Description x
3.1. NCO IP Architectures 3.2. Multichannel NCOs 3.3. Frequency Hopping 3.4. Phase Dithering 3.5. Frequency Modulation 3.6. Phase Modulation 3.7. NCO IP Parameters 3.8. NCO IP Interfaces and Signals
3.1. NCO IP Architectures x
3.1.1. Large ROM Architecture 3.1.2. Small ROM Architecture 3.1.3. CORDIC Architecture 3.1.4. Multiplier-Based Architecture
3.7. NCO IP Parameters x
3.7.1. Architecture Parameters 3.7.2. Frequency Parameters 3.7.3. Optional Ports Parameters
3.8. NCO IP Interfaces and Signals x
3.8.1. Avalon Streaming Interfaces in DSP Intel FPGA IP 3.8.2. NCO IP Signals 3.8.3. NCO IP Timing Diagrams
1. About the NCO IP
2. NCO IP Getting Started
3. NCO IP Functional Description
4. NCO IP User Guide Document Archives
5. Document Revision History for the NCO IP User Guide

1.2. NCO IP Features

  • 32-bit precision for angle and magnitude
  • Source interface compatible with the Avalon Interface Specification
  • Multiple NCO architectures:
    • Multiplier-based implementation using DSP blocks or logic elements (LEs), (single cycle and multi-cycle)
    • Parallel or serial CORDIC-based implementation
    • ROM-based implementation using embedded array blocks (EABs), embedded system blocks (ESBs), or external ROM
  • Single or dual outputs (sine/cosine)
  • Variable width frequency modulation input
  • Variable width phase modulation input
  • User-defined frequency resolution, angular precision, and magnitude precision
  • Frequency hopping
  • Multichannel capability
  • Simulation files and architecture-specific testbenches for VHDL and Verilog HDL
  • Dual-output oscillator and quaternary frequency shift keying (QFSK) modulator example designs
Level Two Title