NCO Intel® FPGA IP User Guide

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ID 683406
Date 10/20/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the NCO IP 2. NCO IP Getting Started 3. NCO IP Functional Description 4. NCO IP User Guide Document Archives 5. Document Revision History for the NCO IP User Guide
1. About the NCO IP x
1.1. DSP Intel® FPGA IP Features 1.2. NCO IP Features 1.3. NCO Intel® FPGA IP Device Family Support 1.4. NCO IP Verification 1.5. NCO IP Release Information
2. NCO IP Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition) 2.4. Simulating Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. NCO IP Core Intel® FPGA IP Evaluation Mode Timeout Behavior
2.3. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition) x
2.3.1. IP Core Generation Output ( Quartus® Prime Pro Edition)
3. NCO IP Functional Description x
3.1. NCO IP Architectures 3.2. Multichannel NCOs 3.3. Frequency Hopping 3.4. Phase Dithering 3.5. Frequency Modulation 3.6. Phase Modulation 3.7. NCO IP Parameters 3.8. NCO IP Interfaces and Signals
3.1. NCO IP Architectures x
3.1.1. Large ROM Architecture 3.1.2. Small ROM Architecture 3.1.3. CORDIC Architecture 3.1.4. Multiplier-Based Architecture
3.7. NCO IP Parameters x
3.7.1. Architecture Parameters 3.7.2. Frequency Parameters 3.7.3. Optional Ports Parameters
3.8. NCO IP Interfaces and Signals x
3.8.1. Avalon Streaming Interfaces in DSP Intel FPGA IP 3.8.2. NCO IP Signals 3.8.3. NCO IP Timing Diagrams
1. About the NCO IP
2. NCO IP Getting Started
3. NCO IP Functional Description
4. NCO IP User Guide Document Archives
5. Document Revision History for the NCO IP User Guide

5. Document Revision History for the NCO IP User Guide

Date Quartus Prime Version IP Version Changes Made
2024.10.20 24.3 19.1.0
  • Removed support for the following devices:
    • Arria II GX
    • Arria II GZ
    • Arria V
    • Cyclone IV
    • Cyclone V
    • MAX 10
    • Stratix IV GT
    • Stratix IV GX/E
    • Stratix V
  • Added support for Agilex devices.
November 2017 2017.11.06 -
  • Deleted reference to MATLAB testbench support
  • Removed design example
  • Added support for Cyclone® 10 devices
  • Changed small ROM architecture description.
  • Corrected "deviation of output values" table position 2.
2014.12.15 14.1 -
  • Added full support for Arria 10 and MAX 10 devices
  • Reordered parameters tables to match wizard
August 2014 14.0 Arria 10 Edition -
  • Added support for Arria 10 devices.
  • Added new in_data and out_data bus descriptions.
  • Added Arria 10 generated files description.
  • Removed table with generated file descriptions.
June 2014 14.0 -
  • Removed device support for Cyclone III and Stratix III devices
  • Added support for MAX 10 FPGAs.
  • Added instructions for using IP Catalog
November 2013 13.1 -
  • Removed support for the following devices:
    • Arria
    • Cyclone I
    • IHardCopy II, HardCopy III, and HardCopy IV
    • Stratix, Stratix II, Stratix GX, and Stratix II GX
  • Added full support for the following devices:
    • Arria V
    • Stratix V
November 2012 12.1 - Added support for Arria V GZ devices.
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