NCO Intel® FPGA IP User Guide

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ID 683406
Date 10/20/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the NCO IP 2. NCO IP Getting Started 3. NCO IP Functional Description 4. NCO IP User Guide Document Archives 5. Document Revision History for the NCO IP User Guide
1. About the NCO IP x
1.1. DSP Intel® FPGA IP Features 1.2. NCO IP Features 1.3. NCO Intel® FPGA IP Device Family Support 1.4. NCO IP Verification 1.5. NCO IP Release Information
2. NCO IP Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition) 2.4. Simulating Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. NCO IP Core Intel® FPGA IP Evaluation Mode Timeout Behavior
2.3. Specifying the IP Parameters and Options ( Quartus® Prime Pro Edition) x
2.3.1. IP Core Generation Output ( Quartus® Prime Pro Edition)
3. NCO IP Functional Description x
3.1. NCO IP Architectures 3.2. Multichannel NCOs 3.3. Frequency Hopping 3.4. Phase Dithering 3.5. Frequency Modulation 3.6. Phase Modulation 3.7. NCO IP Parameters 3.8. NCO IP Interfaces and Signals
3.1. NCO IP Architectures x
3.1.1. Large ROM Architecture 3.1.2. Small ROM Architecture 3.1.3. CORDIC Architecture 3.1.4. Multiplier-Based Architecture
3.7. NCO IP Parameters x
3.7.1. Architecture Parameters 3.7.2. Frequency Parameters 3.7.3. Optional Ports Parameters
3.8. NCO IP Interfaces and Signals x
3.8.1. Avalon Streaming Interfaces in DSP Intel FPGA IP 3.8.2. NCO IP Signals 3.8.3. NCO IP Timing Diagrams
1. About the NCO IP
2. NCO IP Getting Started
3. NCO IP Functional Description
4. NCO IP User Guide Document Archives
5. Document Revision History for the NCO IP User Guide

3.1.4. Multiplier-Based Architecture

The multiplier-based architecture uses multipliers to reduce memory usage. You can choose to implement the multipliers in either:
  • Logic elements (Cyclone series) or combinational ALUTs (Stratix series).
  • Dedicated multiplier circuitry (for example, dedicated DSP blocks) (Stratix or Arria series).
Note: When you specify a dual output multiplier-based NCO, the IP core provides an option to output a sample every two clock cycles. This setting reduces the throughput by a factor of two and halves the resources required by the waveform generation unit.
Table 6.  Architecture Comparison
Architecture Advantages
Large ROM Good for high speed and when a large quantity of internal memory is available. Gives the highest spectral purity and uses the fewest logic elements for a given parameterization.
Small ROM Good for high output frequencies with reduced internal memory usage when a lower SFDR is acceptable.
CORDIC High performance solution when internal memory is at a premium. The serial CORDIC architecture uses fewer resources than parallel although the throughput is reduced.
Multiplier-Based Reduced memory usage by implementing multipliers in logic elements or dedicated circuitry.
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