Intel® MAX® 10 Power Management User Guide

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ID 683400
Date 5/27/2022
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 Power Management Overview 2. Intel® MAX® 10 Power Management Features and Architecture 3. Power Management Controller Reference Design 4. Intel® MAX® 10 Power Management User Guide Archives 5. Document Revision History for the Intel® MAX® 10 Power Management User Guide
2. Intel® MAX® 10 Power Management Features and Architecture x
2.1. Power Supply Device Options 2.2. Power-On Reset Circuitry 2.3. Power Management Controller Scheme 2.4. Hot Socketing
2.1. Power Supply Device Options x
2.1.1. Single-Supply Device 2.1.2. Dual-Supply Device 2.1.3. Comparison of the Intel® MAX® 10 Power Supply Device Options 2.1.4. Power Supply Design
2.1.4. Power Supply Design x
2.1.4.1. Transient Current
2.2. Power-On Reset Circuitry x
2.2.1. Power Supplies Monitored and Not Monitored by the POR Circuitry 2.2.2. Instant-On Support
2.3. Power Management Controller Scheme x
2.3.1. Power Management Controller Architecture
2.3.1. Power Management Controller Architecture x
2.3.1.1. Internal Oscillator 2.3.1.2. I/O Buffer Power Down 2.3.1.3. Global Clock Gating
2.4. Hot Socketing x
2.4.1. Hot-Socketing Specifications 2.4.2. Hot-Socketing Feature Implementation
2.4.1. Hot-Socketing Specifications x
2.4.1.1. Drive Intel® MAX® 10 Devices Before Power Up 2.4.1.2. I/O Pins Remain Tri-stated During Power up
3. Power Management Controller Reference Design x
3.1. Clock Control Block 3.2. I/O Buffer 3.3. Internal Oscillator 3.4. Power Management Controller 3.5. Entering or Exiting Sleep Mode 3.6. Hardware Implementation and Current Measurement
3.4. Power Management Controller x
3.4.1. Entering State 3.4.2. Sleep State 3.4.3. Exiting State 3.4.4. Awake State
3.5. Entering or Exiting Sleep Mode x
3.5.1. Entering Sleep Mode 3.5.2. Exiting Sleep Mode 3.5.3. Timing Parameters
1. Intel® MAX® 10 Power Management Overview
2. Intel® MAX® 10 Power Management Features and Architecture
3. Power Management Controller Reference Design
4. Intel® MAX® 10 Power Management User Guide Archives
5. Document Revision History for the Intel® MAX® 10 Power Management User Guide

2.2.1. Power Supplies Monitored and Not Monitored by the POR Circuitry

Table 4.  Power Supplies Monitored and Not Monitored by the POR Circuitry
Power Supply Device Options Power Supplies Monitored Power Supplies Not Monitored
Single-supply device
  • Regulated VCC_ONE
  • VCCA
  • VCCIO 3
—
Dual-supply device
  • VCC
  • VCCA
  • VCCIO 3
  • VCCD_PLL
  • VCCA_ADC
  • VCCINT

The Intel® MAX® 10 POR circuitry uses an individual POR-detecting circuitry to monitor each of the configuration-related power supplies independently. The outputs of all the individual POR detectors gate the main POR circuitry. The main POR circuitry waits for all individual POR circuitries to release the POR signal before allowing the control block to start configuring the device. The main POR is released after the last ramp-up power reaches the POR trip level followed by a POR delay.

Figure 3. Monitored Power Supplies Ramp Up


Note: Each individual power supply must reach the recommended operating range within the specified tRAMP.
Note: All VCCIO banks must reach the recommended operating level before configuration completes.
Note: The typical value of POR delay is 2.5 ms for Intel® MAX® 10 devices.
Figure 4. Simplified POR Diagram for Intel® MAX® 10 Devices


After the Intel® MAX® 10 device enters user mode, the POR circuit continues to monitor the VCCA and VCC power supplies. This is to detect a brown-out condition during user mode. If either the VCCA or VCC voltages go below the POR trip point during user mode, the main POR signal is asserted. When the main POR signal is asserted, the device is forced into reset state. VCCIO 3 is monitored by the POR circuitry. In the event of the VCCIO 3 voltage drops during user mode, the POR circuit does not reset the device. However, the POR circuit does monitor the VCCIO voltage drop for up to 9 ms after the last power rail reaches its trip point.

3 For banks 1B and 8 for all Intel® MAX® 10 devices and banks 1 and 8 for the 10M02 device.
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