Intel® MAX® 10 Power Management User Guide

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ID 683400
Date 5/27/2022
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 Power Management Overview 2. Intel® MAX® 10 Power Management Features and Architecture 3. Power Management Controller Reference Design 4. Intel® MAX® 10 Power Management User Guide Archives 5. Document Revision History for the Intel® MAX® 10 Power Management User Guide
2. Intel® MAX® 10 Power Management Features and Architecture x
2.1. Power Supply Device Options 2.2. Power-On Reset Circuitry 2.3. Power Management Controller Scheme 2.4. Hot Socketing
2.1. Power Supply Device Options x
2.1.1. Single-Supply Device 2.1.2. Dual-Supply Device 2.1.3. Comparison of the Intel® MAX® 10 Power Supply Device Options 2.1.4. Power Supply Design
2.1.4. Power Supply Design x
2.1.4.1. Transient Current
2.2. Power-On Reset Circuitry x
2.2.1. Power Supplies Monitored and Not Monitored by the POR Circuitry 2.2.2. Instant-On Support
2.3. Power Management Controller Scheme x
2.3.1. Power Management Controller Architecture
2.3.1. Power Management Controller Architecture x
2.3.1.1. Internal Oscillator 2.3.1.2. I/O Buffer Power Down 2.3.1.3. Global Clock Gating
2.4. Hot Socketing x
2.4.1. Hot-Socketing Specifications 2.4.2. Hot-Socketing Feature Implementation
2.4.1. Hot-Socketing Specifications x
2.4.1.1. Drive Intel® MAX® 10 Devices Before Power Up 2.4.1.2. I/O Pins Remain Tri-stated During Power up
3. Power Management Controller Reference Design x
3.1. Clock Control Block 3.2. I/O Buffer 3.3. Internal Oscillator 3.4. Power Management Controller 3.5. Entering or Exiting Sleep Mode 3.6. Hardware Implementation and Current Measurement
3.4. Power Management Controller x
3.4.1. Entering State 3.4.2. Sleep State 3.4.3. Exiting State 3.4.4. Awake State
3.5. Entering or Exiting Sleep Mode x
3.5.1. Entering Sleep Mode 3.5.2. Exiting Sleep Mode 3.5.3. Timing Parameters
1. Intel® MAX® 10 Power Management Overview
2. Intel® MAX® 10 Power Management Features and Architecture
3. Power Management Controller Reference Design
4. Intel® MAX® 10 Power Management User Guide Archives
5. Document Revision History for the Intel® MAX® 10 Power Management User Guide

2.3.1.1. Internal Oscillator

The internal oscillator clocks the power management controller operation. The internal oscillator is routed from flash to the core. The internal oscillator enables the power management controller to detect the wake-up event and the sleep mode event. In order to enable the internal oscillator clock when the power management controller is enabled, you have to set oscena to 1. For the clock frequency of the internal oscillator, refer to the Intel® MAX® 10 FPGA Device Datasheet.

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