Intel® FPGA SDK for OpenCL™ Standard Edition: Custom Platform Toolkit User Guide

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ID 683398
Date 9/24/2018
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform Toolkit User Guide 2. Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform Toolkit Reference Material
1. Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform Toolkit User Guide x
1.1. Prerequisites for the Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform Toolkit 1.2. Overview of the Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform 1.3. Custom Platform Automigration for Forward Compatibility 1.4. Creating an Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform 1.5. Applying for the Intel® FPGA SDK for OpenCL™ Standard Edition Preferred Board Status 1.6. Shipping Recommendations 1.7. Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform Design Revision History
1.2. Overview of the Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform x
1.2.1. Directories and Files in an Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform 1.2.2. Recommendations for Structuring the Custom Platform Directory
1.3. Custom Platform Automigration for Forward Compatibility x
1.3.1. Customizing Automigration
1.4. Creating an Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform x
1.4.1. Designing the Board Hardware 1.4.2. Creating the Board XML Files 1.4.3. Creating the MMD Library 1.4.4. Setting Up the FPGA Client Driver 1.4.5. Providing Intel® FPGA SDK for OpenCL™ Standard Edition Utilities Support 1.4.6. Testing the Hardware Design
1.4.1. Designing the Board Hardware x
1.4.1.1. Creating the Board Platform Designer (Standard) System 1.4.1.2. Establishing Guaranteed Timing Flow
1.4.1.1. Creating the Board Platform Designer (Standard) System x
1.4.1.1.1. General Quality of Results Considerations for the Exported Board Partition
1.4.2. Creating the Board XML Files x
1.4.2.1. Creating the board_env.xml File 1.4.2.2. Creating the board_spec.xml File
1.4.2.1. Creating the board_env.xml File x
1.4.2.1.1. Testing the board_env.xml File
1.4.3. Creating the MMD Library x
1.4.3.1. Kernel Power-up State
2. Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform Toolkit Reference Material x
2.1. The Board Platform Designer (Standard) Subsystem 2.2. XML Elements, Attributes, and Parameters in the board_spec.xml File 2.3. MMD API Descriptions 2.4. Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform Toolkit Reference Manual Revision History
2.1. The Board Platform Designer (Standard) Subsystem x
2.1.1. Intel® FPGA SDK for OpenCL™ Standard Edition-Specific Platform Designer (Standard) System Components
2.1.1. Intel® FPGA SDK for OpenCL™ Standard Edition-Specific Platform Designer (Standard) System Components x
2.1.1.1. OpenCL Kernel Clock Generator 2.1.1.2. OpenCL Kernel Interface 2.1.1.3. OpenCL Memory Bank Divider
2.2. XML Elements, Attributes, and Parameters in the board_spec.xml File x
2.2.1. board 2.2.2. device 2.2.3. global_mem 2.2.4. host 2.2.5. channels 2.2.6. interfaces 2.2.7. interface 2.2.8. compile
2.3. MMD API Descriptions x
2.3.1. aocl_mmd_get_offline_info 2.3.2. aocl_mmd_get_info 2.3.3. aocl_mmd_open 2.3.4. aocl_mmd_close 2.3.5. aocl_mmd_read 2.3.6. aocl_mmd_write 2.3.7. aocl_mmd_copy 2.3.8. aocl_mmd_set_interrupt_handler 2.3.9. aocl_mmd_set_status_handler 2.3.10. aocl_mmd_yield 2.3.11. aocl_mmd_shared_mem_alloc 2.3.12. aocl_mmd_shared_mem_free 2.3.13. aocl_mmd_reprogram 2.3.14. aocl_mmd_hostchannel_create 2.3.15. aocl_mmd_hostchannel_destroy 2.3.16. aocl_mmd_hostchannel_get_buffer 2.3.17. aocl_mmd_hostchannel_ack_buffer
2.3.13. aocl_mmd_reprogram x
2.3.13.1. Reprogram Support
1. Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform Toolkit User Guide
2. Intel® FPGA SDK for OpenCL™ Standard Edition Custom Platform Toolkit Reference Material

1.4.1.1. Creating the Board Platform Designer (Standard) System

When designing your board hardware, you have the option to create a Platform Designer (Standard) subsystem within system.qsys that contains all the board logic. In addition to organizing your design code, having this subsystem allows you to create an Intel® Quartus® Prime partition that you can preserve. To create your board system in a Platform Designer (Standard) subsystem, you may modify the board.qsys template in the Custom Platform Toolkit.

An implementation of a board Platform Designer (Standard) subsystem might include the following components:

  • Proper reset sequencing
  • Intel® FPGA SDK for OpenCL™ Standard Edition-specific components
  • Host-to-FPGA communication IP
  • Memory IP used for SDK's global memory
  • Streaming channels to board-specific interfaces

Refer to The Board Platform Designer (Standard) System section for more information.

Templates of the following hardware design files are available in the INTELFPGAOCLSDKROOT/board/custom_platform_toolkit/board_package/hardware/template directory:

  • board.qsys
  • system.qsys
  • top.v
  • top.qpf
  • board_spec.xml

Template of the post_flow.tcl file is available in the INTELFPGAOCLSDKROOT/board/custom_platform_toolkit/board_package/hardware/template/scripts directory of the Custom Platform Toolkit.

To create nonkernel logic, perform the following tasks in the system.qsys top-level Platform Designer (Standard) system or in a board Platform Designer (Standard) subsystem:

  1. In Platform Designer (Standard), add your host and memory IPs to the Platform Designer (Standard) system, and establish all necessary connections and exports.
    Attention: You might need to acquire separate IP licenses. For a list of available licensed and unlicensed IP solutions, visit the All Intellectual Property page of the Intel® FPGA website. For more information about each IP, click the link in the Product Name column to navigate to the product page.
    1. Connect your host interface clock such that it drives por_reset_controller/clk. Your design's global reset and clock inputs are fed to a reset counter (por_reset_counter). This reset counter then synchronizes to the host interface clock in the Merlin Reset Controller (por_reset_controller).
      The por_reset_counter ACL SW Reset component implements the power-on reset. It resets all the device hardware by issuing a reset for a number of cycles after the FPGA completes its configuration.
    2. Modify the parameters of the pipe_stage_host_ctrl Avalon® Memory-Mapped (Avalon-MM) Pipeline Bridge component such that it can receive requests from your host IP. Connect your host interface's Avalon-MM master port to the s0 port of pipe_stage_host_ctrl. Connect the m0 port of pipe_stage_host_ctrl to all the peripherals that must communicate with your host interface, including the OpenCL Kernel Clock Generator and the OpenCL Kernel Interface components.
    3. Adjust the number of clock_cross_kernel_mem_<N> Avalon-MM Clock Crossing Bridge components to match the number of memory interfaces on your board. This component performs clock crossing between the kernel and memory interfaces. Modify the parameters of each component so that they are consistent with the parameters of the OpenCL Memory Bank Divider component and the interface attribute described in board_spec.xml. Connect the m0 master, clock, and reset ports of clock_cross_kernel_mem_<N> (that is, m0, m0_clk, and m0_reset, respectively) to your memory IP.
      Important: Connect m0_reset in such a way that assertion of kernel_reset from the OpenCL Memory Bank Divider component triggers this reset.
  2. Customize the SDK-specific Platform Designer (Standard) system components..
    Attention: If you use the board.qsys system template to create a Platform Designer (Standard) subsystem, note that it is preconfigured with the necessary connections between the SDK-specific system components and the appropriate interfaces exported to match the board_spec.xml file. Intel® recommends that you preserve the preconfigured connections as much as possible.
    1. In Platform Designer (Standard), click Tools > Options. In the Options dialog box, add INTELFPGAOCLSDKROOT/ip/board to the Qsys IP Search Path and then click Finish.
    2. Instantiate the OpenCL Kernel Clock Generator component. Specify the component parameters, and connect the signals and ports as outlined in the OpenCL Kernel Clock Generator section.
    3. Instantiate the OpenCL Kernel Interface component. Specify the component parameters, and connect the signals and ports as outlined in the OpenCL Kernel Interface section.
    4. For each global memory type, instantiate the OpenCL Memory Bank Divider component. Specify the component parameters, and connect the signals and ports as outlined in the OpenCL Memory Bank Divider section.
      Attention: Set the parameters such that the resulting bank masters have the equivalent address bits and burst widths as those from the kernel, as defined in the interface attribute of the global_mem element in the board_spec.xml file. For each memory bank, Platform Designer (Standard) generates a master that inherits the same characteristics as your specifications.
  3. If you choose to create a Platform Designer (Standard) subsystem for the nonkernel logic, export any necessary I/Os to the top-level system.qsys Platform Designer (Standard) system.
  4. Edit the top-level top.v file to instantiate system.qsys and connect any board-specific I/Os.
  5. Set up the top.qpf Intel® Quartus® Prime project with all the necessary settings for your board design.
  6. Modify the post_flow.tcl file to include the Tcl code that generates the fpga.bin file during Intel® Quartus® Prime compilation.
    The fpga.bin file is necessary for programming the board.
  7. Edit the board_spec.xml file to include board-specific descriptions.

Section Content
General Quality of Results Considerations for the Exported Board Partition

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