When a processor with a data cache issues a read and the data is not in the cache, the cache will load a small block or ‘line’ of data from memory into the cache. When the processor issues a write, the new value is stored in the data cache. With a write back data cache as in the Nios II processor, new data values are only written back to the real physical location when the cache is flushed or data is evicted from the cache. This kind of operation is not acceptable for regions of memory where the data must be written immediately to the hardware to affect the function/operation desired such as shared memory or writes to peripheral/hardware control registers. You are required to either flush the cache immediately, or use a memory operation that bypasses the cache and goes directly to the hardware preferred. Sometimes there may be other reasons why you don't want the data to be cached (e.g. if the data is never to be read back and/or it is not desirable to evict other data from the cache for performance or other reasons).

With the Nios II Classic processor cache bypass can be achieved by using special I/O read/write instructions (e.g. ldwio/stwio), by setting bit-31 of the data read/write address, or by implementing an MMU/MPU and setting it up appropriately.

If the Nios II Classic processor performs an uncached write and the memory location (and hence associated cache line) is present in the data cache, the new data value is also written to the cache despite this being an uncached write. This means that the data in the cache is always up to date, and if the software design causes data from locations that have been subject to uncached memory writes to be loaded from the cache, there is no loss of data coherency. Hence the Nios II Classic processor can support uncached memory regions of any size and any address alignment as it allows mixing of cached and uncached regions of memory on the same cache line. This is not true for Nios II Gen2 cores.

In the Nios II Gen2 processor core, uncached transactions truly bypass the data cache and the cache contents are not updated (standard practice for most processors). If an uncached memory region shares a cache line with a cached region, the uncached region will be mapped into the cache and the memory may be updated with useless data when the cache is flushed. You have to ensure that uncached and cached memory regions are clearly separated and do not share the same cache line when mapped into the data cache. This is achieved by ensuring that uncached memory regions are aligned to the size of the data cache line (32 bytes) and are the size of one or more data cache lines (multiples of 32 bytes). This prevents mixing of cacheable and non-cacheable data on the same cache line and hence write back of stale/invalid data. Altera recommends that base addresses of peripheral register sets are aligned with the data cache line boundaries and that drivers use the cache bypass I/O read write instructions. So it is unlikely that modifications to drivers will be required. Other software that uses cache bypass/uncached memory regions should be checked carefully to ensure that cache lines do not map to regions containing both cached and uncached data.

You should consider the potential effects of using the new 32-bit address range and peripheral memory region options if the hardware configuration is changed to use them. The software should be modified to support these features or detect them and issue error messages.

The HAL and Linux driver code has all been updated so as long as a new BSP has been generated and compiled there will be no issues with the Nios II software libraries.