LDPC IP Core User Guide

ID 683381
Date 4/04/2022
Public

4.1.3. LDPC IP Core Signals

Table 11.  Avalon-ST Input and Output Interface Signals
Name Avalon-ST Type Direction Description
in_data[] data Input Data input for each codeword. Valid only when you assert the in_valid signal. In Qsys systems, this Avalon-ST compliant data bus includes all the Avalon-ST input data signals.
in_endofpacket eop Input End of packet (codeword) signal.
in_number - Input

Variable rate DOCSIS only. in_number is active at SOP. It is a 3-bit signal

  • 001 for large frame (rate=0.89)
  • 010 for medium frame (rate=0.85)
  • 100 for short frame (rate=0.75)
in_rate - Input

Variable rate WiMedia only. in_rate is active at SOP. It is a 4-bit width signal:

  • 0001 corresponds to code rate 0.8
  • 0010 corresponds to code rate 0.75
  • 0100 corresponds to code rate 0.625
  • 1000 corresponds to code rate 0.5
in_ready ready Output Data transfer ready signal to indicate that the sink is ready to accept data. The sink interface drives the in_ready signal to control the flow of data across the interface. The sink interface captures the data interface signals on the current clk rising edge.
in_startofpacket sop Input Start of packet (codeword) signal.
in_valid valid Input Data valid signal to indicate the validity of the data signals. When you assert the in_valid signal, the Avalon-ST data interface signals are valid. When you deassert the in_valid signal, the Avalon-ST data interface signals are invalid and must be disregarded. You can assert the in_valid signal whenever data is available. However, the sink only captures the data from the source when the IP core asserts the in_ready signal.
out_data data Output The out_data signal contains decoded output when the IP core asserts the out_valid signal. The corrected symbols are in the same order that they are entered.
out_endofpacket eop Output End of packet (codeword) signal. This signal indicates the packet boundaries on the in_data[] bus. When the IP core drives this signal high, it indicates that the end of packet is present on the in_data[] bus. The IP core asserts this signal on the last transfer of every packet.
out_startofpacket sop Output Start of packet (codeword) signal. This signal indicates the codeword boundaries on the in_data[] bus. When the IP core drives this signal high, it indicates that the start of packet is present on the in_data[] bus. The IP core asserts this signal on the first transfer of every codeword.
out_ready ready Input Data transfer ready signal to indicate that the downstream module is ready to accept data. The source provides new data (if available) when you assert the out_ready signal and stops providing new data when you deassert the out_ready signal. If the source is unable to provide new data, it deasserts out_valid for one or more clock cycles until it is prepared to drive valid data interface signals.
out_valid valid Output Data valid signal. The IP core asserts the out_valid signal high, whenever there is a valid output on out_data ; the IP core deasserts the signal when there is no valid output on out_data .

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