LDPC IP Core User Guide

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ID 683381
Date 4/04/2022
Public
Document Table of Contents
Document Table of Contents x
Product Discontinuance Notification 2. LDPC IP EOL 2. About the LDPC IP Core 3. Getting Started with the LDPC IP Core 4. LDPC IP Core Specifications 5. Document Revision History A. LDPC IP Core Document Archive
2. About the LDPC IP Core x
2.1. LDPC IP Core Features 2.2. LDPC IP Device Family Support 2.3. LDPC IP Core Release Information 2.4. DSP Intel® FPGA IP Verification 2.5. LDPC IP Core Performance
3. Getting Started with the LDPC IP Core x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. IP Catalog and Parameter Editor 3.3. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) 3.4. Simulating Intel® FPGA IP Cores
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel® FPGA IP Evaluation Mode 3.1.2. LDPC IP Core Intel® FPGA IP Evaluation Mode Timeout Behavior
3.3. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) x
3.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
4. LDPC IP Core Specifications x
4.1. LDPC IP Core Interfaces 4.2. LDPC IP Core Parameters
4.1. LDPC IP Core Interfaces x
4.1.1. Avalon Streaming Interfaces in DSP Intel FPGA IP 4.1.2. Clock and Reset Interfaces 4.1.3. LDPC IP Core Signals
4.1.3. LDPC IP Core Signals x
4.1.3.1. LDPC IP Core Backpressure
Product Discontinuance Notification
2. LDPC IP EOL
2. About the LDPC IP Core
3. Getting Started with the LDPC IP Core
4. LDPC IP Core Specifications
5. Document Revision History
A. LDPC IP Core Document Archive

1.4. DSP IP Core Verification

Before releasing a version of an IP core, Intel runs comprehensive regression tests to verify its quality and correctness. Intel generates custom variations of the IP core to exercise the various parameter options and thoroughly simulates the resulting simulation models with the results verified against master simulation models.
Level Two Title