FFT IP Core: User Guide

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ID 683374
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
1. About This IP Core 2. FFT IP Core Getting Started 3. FFT IP Core Functional Description 4. Block Floating Point Scaling 5. Document Revision History A. FFT IP Core User Guide Document Archive
1. About This IP Core x
1.1. Intel® DSP IP Core Features 1.2. FFT IP Core Features 1.3. General Description 1.4. DSP IP Core Device Family Support 1.5. DSP IP Core Verification 1.6. FFT IP Core Release Information 1.7. Performance and Resource Utilization
1.3. General Description x
1.3.1. Fixed Transform Size FFT 1.3.2. Variable Streaming FFT
2. FFT IP Core Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) 2.4. Generating IP Cores ( Intel® Quartus® Prime Standard Edition) 2.5. Simulating Intel® FPGA IP Cores 2.6. DSP Builder for Intel® FPGAs Design Flow
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. FFT IP Core Intel® FPGA IP Evaluation Mode Timeout Behavior
2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
2.4. Generating IP Cores ( Intel® Quartus® Prime Standard Edition) x
2.4.1. IP Core Generation Output ( Intel® Quartus® Prime Standard Edition)
2.5. Simulating Intel® FPGA IP Cores x
2.5.1. Simulating the Fixed-Transform FFT IP Core in the MATLAB Software 2.5.2. Simulating the Variable Streaming FFT IP Core in the MATLAB Software
3. FFT IP Core Functional Description x
3.1. Fixed Transform FFTs 3.2. Variable Streaming FFTs 3.3. FFT Processor Engines 3.4. I/O Data Flow 3.5. FFT IP Core Parameters 3.6. FFT IP Core Interfaces and Signals
3.2. Variable Streaming FFTs x
3.2.1. Fixed-Point Variable Streaming FFTs 3.2.2. Floating-Point Variable Streaming FFTs
3.3. FFT Processor Engines x
3.3.1. Quad-Output FFT Engine 3.3.2. Single-Output FFT Engine
3.4. I/O Data Flow x
3.4.1. Streaming FFT 3.4.2. Variable Streaming 3.4.3. Buffered Burst 3.4.4. Burst
3.4.1. Streaming FFT x
3.4.1.1. Using the Streaming FFT 3.4.1.2. Changing the Direction on a Block-by-Block Basis 3.4.1.3. Enabling the Streaming FFT
3.4.2. Variable Streaming x
3.4.2.1. Changing Block Size 3.4.2.2. Changing Direction 3.4.2.3. I/O Order 3.4.2.4. Enabling the Variable Streaming FFT 3.4.2.5. Dynamically Changing the FFT Size 3.4.2.6. I/O Order
3.4.3. Buffered Burst x
3.4.3.1. Enabling the Buffered Burst FFT
3.6. FFT IP Core Interfaces and Signals x
3.6.1. Avalon-ST Interfaces in DSP IP Cores 3.6.2. FFT IP Core Avalon-ST Signals
3.6.2. FFT IP Core Avalon-ST Signals x
3.6.2.1. Component Specific Signals
4. Block Floating Point Scaling x
4.1. Possible Exponent Values 4.2. Implementing Scaling 4.3. Unity Gain in an IFFT+FFT Pair
4.2. Implementing Scaling x
4.2.1. Example of Scaling
1. About This IP Core
2. FFT IP Core Getting Started
3. FFT IP Core Functional Description
4. Block Floating Point Scaling
5. Document Revision History
A. FFT IP Core User Guide Document Archive

3.6.2. FFT IP Core Avalon-ST Signals

Table 10.  Avalon-ST Signals
Signal Name Direction Avalon-ST Type Size Description
clk Input clk 1 Clock signal that clocks all internal FFT engine components.
reset_n Input reset_n 1 Active-low asynchronous reset signal.This signal can be asserted asynchronously, but must remain asserted at least one clk clock cycle and must be deasserted synchronously with clk.
sink_eop Input endofpacket 1 Indicates the end of the incoming FFT frame.
sink_error Input error 2 Indicates an error has occurred in an upstream module, because of an illegal usage of the Avalon-ST protocol. The following errors are defined:
  • 00 = no error
  • 01 = missing start of packet (SOP)
  • 10 = missing end of packet (EOP)
  • 11 = unexpected EOP

    If this signal is not used in upstream modules, set to zero.
sink_imag Input data data precision width Imaginary input data, which represents a signed number of data precision bits.
sink_ready Output ready 1 Asserted by the FFT engine when it can accept data. It is not mandatory to provide data to the FFT during ready cycles.
sink_real Input data data precision width Real input data, which represents a signed number of data precision bits.
sink_sop Input startofpacket 1 Indicates the start of the incoming FFT frame.
sink_valid Input valid 1 Asserted when data on the data bus is valid. When sink_valid and sink_ready are asserted, a data transfer takes place..
sink_data Input data Variable

In Qsys systems, this Avalon-ST-compliant data bus includes all the Avalon-ST input data signals from MSB to LSB:

  • sink_real
  • sink_imag
  • fftpts_in
  • inverse
source_eop Output endofpacket 1 Marks the end of the outgoing FFT frame. Only valid when source_valid is asserted.
source_error Output error 2 Indicates an error has occurred either in an upstream module or within the FFT module (logical OR of sink_error with errors generated in the FFT).
source_exp Output data 6 Streaming, burst, and buffered burst FFTs only. Signed block exponent: Accounts for scaling of internal signal values during FFT computation.
source_imag Output data (data precision width + growth) Imaginary output data. For burst, buffered burst, streaming, and variable streaming floating point FFTs, the output data width is equal to the input data width. For variable streaming fixed point FFTs, the size of the output data is dependent on the number of stages defined for the FFT and is 2 bits per radix 22 stage.
source_ready Input ready 1 Asserted by the downstream module if it is able to accept data.
source_real Output data (data precision width + growth) Real output data. For burst, buffered burst, streaming, and variable streaming floating point FFTs, the output data width is equal to the input data width. For variable streaming fixed point FFTs, the size of the output data is dependent on the number of stages defined for the FFT and is 2 bits per radix 22 stage. Variable streaming fixed point FFT only. Growth is log2(N)+1.
source_sop Output startofpacket 1 Marks the start of the outgoing FFT frame. Only valid when source_valid is asserted.
source_valid Output valid 1 Asserted by the FFT when there is valid data to output.
source_data Output data Variable

In Qsys systems, this Avalon-ST-compliant data bus includes all the Avalon-ST output data signals from MSB to LSB:

  • source_real
  • source_imag
  • fftpts_out

Section Content
Component Specific Signals

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