F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683372
Date 4/07/2025
Public
Document Table of Contents

3.3.1.5. Steps to Run Simulation : Riviera-PRO*

Simulation Flow starting with Quartus® Prime 22.4 version

  1. Generate the example design
  2. Follow the steps below:
    1. cd <my_design>/pcie_ed_sim_tb/pcie_ed_sim_tb/sim/aldec
    2. Run the following command from the working directory:
      vsim -do run_riviera.tcl
    3. A successful simulation ends with the following message:
      "Simulation stopped due to successful completion!"