F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
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2.1.2. Programmed Input/Output Design Example Limitation
For the PIO design example, there is no support for the back-to-back TLP packets from the host processor.
The design example is intended to handle simple read-write instructions based on the TLP command. TLP transaction of memory write request (MWr) and write the data to the MEM device. As for the TLP transaction of memory read request (MRd), the design will read the data from the MEM device and return completion with data (CplD).