F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683372
Date 2/03/2023
Public

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2.1.1.2.1. Scheduler

The data stream from DUT is buffered in the data FIFO within the scheduler block. The header will be pre-processed to and calculate some prerequisite values. It will pass the command to Read Write Module after precalculated the write burst count and write First DWORD Byte Enable and Last DWORD Byte Enable from the header information.
  • Write sequence: The data in the data FIFO is forwarded to Read Write Module.
  • Read sequence: Read TLP attributes to generate the completion TLP and additional processing to determine the Type1 read and Type2 read. When the TLP DW length is less than Max Payload Size boundary, Type1 read is initiated. When TLP DW length is larger than Max Payload Size boundary, the Type2 read is initiated. Each Type1 and Type2 read could only hold up to the size of its MPS. No data in the data FIFO is forwarded to the Read Write Module since this is a read sequence. Only the pre-processed commands are forwarded to the pre-processed command FIFO for Avalon-MM generation in the Read Write Module.