F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 683372
Date 10/04/2021
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Document Table of Contents
Document Table of Contents x
1. Acronyms 2. Design Example Description 3. Quick Start Guide 4. F-Tile Avalon Streaming Intel FPGA IP for PCI Express Design Example User Guide Archives 5. Revision History for the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
2. Design Example Description x
2.1. Programmed Input/Output Design Example 2.2. Programmed Input/Output Design Example Functional Description 2.3. Programmed Input/Output Design Example Simulation Testbench
2.2. Programmed Input/Output Design Example Functional Description x
2.2.1. F-Tile Avalon-ST IP for PCI Express Hard IP (DUT) 2.2.2. PIO Application (APPS) 2.2.3. On-Chip Memory (MEM) 2.2.4. F-Tile Reference and System PLL Clocks IP 2.2.5. Reset Release IP
2.2.2. PIO Application (APPS) x
2.2.2.1. Scheduler 2.2.2.2. Read Write Module 2.2.2.3. Avalon-MM Interface 2.2.2.4. Completion Module 2.2.2.5. Width Adapter
3. Quick Start Guide x
3.1. Directory Structure 3.2. Generating the Design Example 3.3. Simulating the Design Example 3.4. Compiling the Design Example 3.5. Installing the Linux Kernel Driver 3.6. Running the Design Example
3.3. Simulating the Design Example x
3.3.1. Testbench
3.3.1. Testbench x
3.3.1.1. Test Driver Module
3.3.1.1. Test Driver Module x
3.3.1.1.1. PIO Design Example Testbench
3.6. Running the Design Example x
3.6.1. Running the PIO Design Example
1. Acronyms
2. Design Example Description
3. Quick Start Guide
4. F-Tile Avalon Streaming Intel FPGA IP for PCI Express Design Example User Guide Archives
5. Revision History for the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

2.3. Programmed Input/Output Design Example Simulation Testbench

The simulation testbench instantiates the PIO design example and a Root Port BFM to interface with the target Endpoint.

Figure 7. Block Diagram for the PCIe x16 PIO Design Example Simulation Testbench
Figure 8. Block Diagram for the PCIe x8x8 PIO Design Example Simulation Testbench
Note: The simulation testbench for PCIe x8x8 PIO Design Example is configured for a single PCIe x8 link although the actual design implements two PCIe x8 links.
Figure 9. Block Diagram for the PCIe x8 PIO Design Example Simulation Testbench

The test program writes to and reads back data from the same location in the on-chip memory. It compares the data read to the expected result. The test reports, "Simulation stopped due to successful completion" if no errors occur.

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