F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 683372
Date 10/04/2021
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Document Table of Contents
Document Table of Contents x
1. Acronyms 2. Design Example Description 3. Quick Start Guide 4. F-Tile Avalon Streaming Intel FPGA IP for PCI Express Design Example User Guide Archives 5. Revision History for the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide
2. Design Example Description x
2.1. Programmed Input/Output Design Example 2.2. Programmed Input/Output Design Example Functional Description 2.3. Programmed Input/Output Design Example Simulation Testbench
2.2. Programmed Input/Output Design Example Functional Description x
2.2.1. F-Tile Avalon-ST IP for PCI Express Hard IP (DUT) 2.2.2. PIO Application (APPS) 2.2.3. On-Chip Memory (MEM) 2.2.4. F-Tile Reference and System PLL Clocks IP 2.2.5. Reset Release IP
2.2.2. PIO Application (APPS) x
2.2.2.1. Scheduler 2.2.2.2. Read Write Module 2.2.2.3. Avalon-MM Interface 2.2.2.4. Completion Module 2.2.2.5. Width Adapter
3. Quick Start Guide x
3.1. Directory Structure 3.2. Generating the Design Example 3.3. Simulating the Design Example 3.4. Compiling the Design Example 3.5. Installing the Linux Kernel Driver 3.6. Running the Design Example
3.3. Simulating the Design Example x
3.3.1. Testbench
3.3.1. Testbench x
3.3.1.1. Test Driver Module
3.3.1.1. Test Driver Module x
3.3.1.1.1. PIO Design Example Testbench
3.6. Running the Design Example x
3.6.1. Running the PIO Design Example
1. Acronyms
2. Design Example Description
3. Quick Start Guide
4. F-Tile Avalon Streaming Intel FPGA IP for PCI Express Design Example User Guide Archives
5. Revision History for the F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Design Example User Guide

2.2.2. PIO Application (APPS)

The PIO Application (APPS) component performs the necessary translation between the PCI Express TLPs and simple Avalon-MM writes and reads to the onchip memory. The PIO component interfaces between the Avalon-ST and Avalon- MM. It decodes the TLP headers/data and converts it into Avalon-MM compatible instructions. For a write operation, a single write data TLP is converted into a single AVMM write instruction. While for the read operation, it could be multiple data read back depending on the max payload size boundary. It reads and writes in 512 bits and support contiguous byte enables. These operations are done in the Bursting Avalon Master module in the PIO Application which consists of 4 sub-modules, namely the Scheduler, Read Write Module, Avalon-MM Interface and Completion Module.

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