SDI II Intel® Stratix 10 FPGA IP Design Example User Guide

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ID 683368
Date 12/09/2022
Public
Document Table of Contents
Document Table of Contents x
1. SDI II Intel® FPGA IP Design Example Quick Start Guide 2. SDI II Intel® FPGA IP Design Example Detailed Description 3. SDI II Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 4. Document Revision History for the SDI II Intel® Stratix® 10 FPGA IP Design Example User Guide
1. SDI II Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. SDI II Intel® FPGA Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Connection and Settings Guidelines 1.5.2. Design Considerations
1.6. SDI II Intel® FPGA Design Example Parameters x
1.6.1. Design Example Presets
2. SDI II Intel® FPGA IP Design Example Detailed Description x
2.1. Parallel Loopback Design Examples 2.2. Serial Loopback Design Examples 2.3. Design Components 2.4. Clocking Scheme Signals 2.5. Interface Signals 2.6. Video Pattern Generator Parameters 2.7. Hardware Setup 2.8. Simulation Testbench 2.9. Upgrading Your Design
1. SDI II Intel® FPGA IP Design Example Quick Start Guide
2. SDI II Intel® FPGA IP Design Example Detailed Description
3. SDI II Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
4. Document Revision History for the SDI II Intel® Stratix® 10 FPGA IP Design Example User Guide

1.1. Directory Structure

The directories contain the generated files for the design examples.
Figure 2. Directory Structure for the Design Examples
Table 1.  Other Generated Files in RTL Folder
Folders Files
vid_pattgen /sdi_ii_colorbar_gen.v
/sdi_ii_ed_vid_pattgen.v
/sdi_ii_makeframe.v
/sdi_ii_patho_gen.v
/jtag.sdc
/pattgen_ctrl.qsys
<qsys generated folder>
loopback /loopback_top.v
/fifo/sdi_ii_ed_loopback.sdc
/fifo/sdi_ii_ed_loopback.v
/pfd/clock_crossing.v (optional)
/pfd/pfd.sdc (optional)
/pfd/pfd.v (optional)
/reclock/sdi_reclock.v (optional)
/reclock/pid_controller.v (optional)
/reclock/rcfg_pll_frac.v (optional)
du /du_top.v
/sdi_ii_rx_rcfg_s10.sv (optional)
/rcfg_sdi_cdr.sv (optional)
/rcfg_pll_sw.sv (optional)
/rcfg_refclk_sw.sv (optional)
/sdi_ii_tx_rcfg_s10.sv (optional)
/sdi_du_sys.qsys
/sdi_rx_phy.ip
/tx_pll.ip
/tx_pll_alt.ip (optional)
<qsys generated folder>
rx /rx_top.v
/sdi_ii_rx_rcfg_s10.sv (optional)
/rcfg_sdi_cdr.sv (optional)
/sdi_rx_sys.qsys
<qsys generated folder>
tx /tx_top.v
/rcfg_pll_sw.sv (optional)
/rcfg_refclk_sw.sv (optional)
/sdi_ii_tx_rcfg_s10.sv (optional)
/sdi_tx_sys.qsys
/tx_pll.ip
/tx_pll_alt.ip(optional)
<qsys generated folder>
mr_phy_adapter /sdi_s10_mr_phy_adapter.v
/rxdata_mwfifo.ip
/txdata_mwfifo.ip
<qsys generated folder>
Table 2.   Other Generated Files in Simulation Folder
Folders Files
aldec /aldec.do
/rivierapro_setup.tcl
common /modelsim_files.tcl
/riviera_files.tcl
/vcs_files.tcl
/vcsmx_files.tcl
/xcelium_files.tcl
mentor /mentor.do
/msim_setup.tcl
synopsys /vcs/filelist.f
/vcs/vcs_setup.sh
/vcs/vcs_sim.sh
/vcsmx/synopsys_sim_setup
/vcsmx/vcsmx_setup.sh
/vcsmx/vcsmx_sim.sh
testbench tb_top.v
rx_checker/sdi_ii_tb_rx_checker.v
rx_checker/tb_data_compare.v
rx_checker/tb_dual_link_sync.v
rx_checker/tb_fifo_line_test.v
rx_checker/tb_frame_locked_test.sv
rx_checker/tb_ln_check.v
rx_checker/tb_rxsample_test.v
rx_checker/tb_trs_locked_test.sv
rx_checker/tb_txpll_test.sv
rx_checker/tb_vpid_check.v
tb_control/sdi_ii_tb_control.v
tb_control/tb_clk_rst.v
tb_control/tb_data_delay.v
tb_control/tb_serial_delay.sv
tb_control/tb_tasks.v
tb_checker/sdi_ii_tb_tx_checker.v
tb_checker/tb_serial_check_counter.v
tb_checker/tb_serial_descrambler.v
tb_checker/tb_tx_clkout_check.v
vid_pattgen/sdi_ii_colorbar_gen.v
vid_pattgen/sdi_ii_ed_vid_pattgen.v
vid_pattgen/sdi_ii_makeframe.v
vid_pattgen/sdi_ii_patho_gen.v
xcelium /cds.lib
/hdl.var
/xcelium_setup.sh
/xcelium_sim.sh
<cds_libs folder>
Level Two Title