Unified FFT IPs User Guide

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ID 683366
Date 3/26/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the Unified FFT IPs 2. Getting Started with the Unified FFT IP 3. Bit-Reverse IP 4. FFT IP 5. Parallel FFT IP 6. Variable Size Bit-Reverse IP 7. Variable Size FFT IP 8. Unified FFT IPs User Guide Archive 9. Document Revision History for the Unified FFT IPs User Guide
1. About the Unified FFT IPs x
1.1. Features of the Unified FFT IPs 1.2. Unified FFT IPs Device Family Support 1.3. Release Information for the Unified FFT IPs 1.4. Supported Data Types 1.5. FFT Spectrum 1.6. Global Enable
2. Getting Started with the Unified FFT IP x
2.1. IP Installation and Licensing 2.2. Generating a Unified FFT IP 2.3. Compiling the Software Model for the Unified FFT IPs 2.4. Running the Unified FFT IPs Automatic Testbench
1. About the Unified FFT IPs
2. Getting Started with the Unified FFT IP
3. Bit-Reverse IP
4. FFT IP
5. Parallel FFT IP
6. Variable Size Bit-Reverse IP
7. Variable Size FFT IP
8. Unified FFT IPs User Guide Archive
9. Document Revision History for the Unified FFT IPs User Guide

1.6. Global Enable

You may specify an optional global enable signal for all Unified FFT IPs.

When a global enable signal is present, you enable the IPs when the signal is high and disable them when the signal is low. When you disable an IP, the externally visible state of the IP freezes in its last state when it was enabled. The IP ignores all inputs when it is disabled. When the IP is re-enabled it continues as if nothing happened while it was disabled.

Level Two Title