Unified FFT Intel® FPGA IPs User Guide

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ID 683366
Date 3/06/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the Unified FFT Intel FPGA IPs 2. Getting Started with the Unified FFT Intel FPGA IP 3. Bit-reverse Intel® FPGA IP 4. FFT Intel FPGA IP 5. Parallel FFT Intel FPGA IP 6. Variable Size Bit-reverse Intel FPGA IP 7. Variable Size FFT Intel FPGA IP 8. Unified FFT Intel FPGA IPs User Guide Archive 9. Document Revision History for the Unified FFT Intel FPGA IPs User Guide
1. About the Unified FFT Intel FPGA IPs x
1.1. Features of the Unified FFT Intel FPGA IPs 1.2. Unified FFT Intel FPGA IPs Device Family Support 1.3. Release Information for the Unified FFT IPs 1.4. Supported Data Types 1.5. FFT Spectrum 1.6. Global Enable
2. Getting Started with the Unified FFT Intel FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Generating a Unified FFT IP 2.3. Compiling the Software Model for the Unified FFT IPs 2.4. Running the Unified FFT IPs Automatic Testbench
1. About the Unified FFT Intel FPGA IPs
2. Getting Started with the Unified FFT Intel FPGA IP
3. Bit-reverse Intel® FPGA IP
4. FFT Intel FPGA IP
5. Parallel FFT Intel FPGA IP
6. Variable Size Bit-reverse Intel FPGA IP
7. Variable Size FFT Intel FPGA IP
8. Unified FFT Intel FPGA IPs User Guide Archive
9. Document Revision History for the Unified FFT Intel FPGA IPs User Guide

9. Document Revision History for the Unified FFT Intel FPGA IPs User Guide

Document Version IP Version Quartus® Prime Version Changes
2025.03.06 1.0.8 24.1 Added the following statement to Generate a Global Enable Signal :The input valid may be deasserted during an FFT iteration when the IP is disabled. For more information about the global enable, refer to Global Enable.
2025.02.18   24.1
  • Removed "This signal must not deassert during an FFT. Keep it asserted from the first input to last input of an FFT" from validIn in Bit-reverse Intel FPGA IP Input Signals and Variable Size Bit-reverse Intel FPGA IP Input Signals
  • Added "You must supply all the input data required for a single FFT iteration (one block) on consecutive clocks cycles, but an arbitrary large (or small) gap can exist between consecutive blocks." to :
    • FFT Intel FPGA IP
    • Parallel FFT Intel FPGA IP
    • Variable Size FFT Intel FPGA IP
2024.06.17 1.0.8 24.1 Added support for Agilex 5 devices
2023.09.30 1.0.7 23.3
  • Updated the product family name to "Intel Agilex 7."
  • Updated Compiling the Software Model for the Unified FFTs
2021.04.05 - 21.1 Added:
  • Release Information
  • User Guide Archive
  • Supported Datatypes
  • FFT Spectrum
  • Global Enable
  • Generate a cycle-accurate software model parameter
  • Example use of the Variable Size Bit-reverse Intel FPGA IP figure
2020.10.05 1.0.0 20.3 Initial release.
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