Unified FFT Intel FPGA IPs User Guide

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ID 683366
Date 9/30/2023
Public

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Document Table of Contents
Document Table of Contents x
1. About the Unified FFT Intel FPGA IPs 2. Getting Started with the Unified FFT Intel FPGA IP 3. Bit-reverse Intel® FPGA IP 4. FFT Intel FPGA IP 5. Parallel FFT Intel FPGA IP 6. Variable Size Bit-reverse Intel FPGA IP 7. Variable Size FFT Intel FPGA IP 8. Unified FFT Intel FPGA IPs User Guide Archive 9. Document Revision History for the Unified FFT Intel FPGA IPs User Guide
1. About the Unified FFT Intel FPGA IPs x
1.1. Features of the Unified FFT Intel FPGA IPs 1.2. Unified FFT Intel FPGA IPs Device Family Support 1.3. Release Information for the Unified FFT IPs 1.4. Supported Data Types 1.5. FFT Spectrum 1.6. Global Enable
2. Getting Started with the Unified FFT Intel FPGA IP x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Generating a Unified FFT IP 2.3. Compiling the Software Model for the Unified FFT IPs 2.4. Running the Unified FFT IPs Automatic Testbench
1. About the Unified FFT Intel FPGA IPs
2. Getting Started with the Unified FFT Intel FPGA IP
3. Bit-reverse Intel® FPGA IP
4. FFT Intel FPGA IP
5. Parallel FFT Intel FPGA IP
6. Variable Size Bit-reverse Intel FPGA IP
7. Variable Size FFT Intel FPGA IP
8. Unified FFT Intel FPGA IPs User Guide Archive
9. Document Revision History for the Unified FFT Intel FPGA IPs User Guide

8. Unified FFT Intel FPGA IPs User Guide Archive

For the latest and previous versions of this document, refer to: Unified FFT Intel FPGA IP User Guide. If an IP or software version is not listed, the user guide for the previous IP or software version applies.

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